標題: VLSI IMPLEMENTATION OF AN M-ARRAY IMAGE FILTER BASED ON SHIFT REGISTER ARRAY
作者: LEE, CY
TSAI, JM
HSU, SC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: MEDIAN FILTERING;M-ARRAY;SHIFT REGISTER ARRAY;LEVEL CONTROL
公開日期: 1-十一月-1993
摘要: This paper presents a novel VLSI solution for sorting input samples in the transform domain to achieve real-time performance for image/video applications. The sorting is based on a dedicated memory containing so-called bar-chart information. The required value, such as median, can be generated from MSB to LSB sequentially by successively evaluating each bit of the memory content. In the architecture design, the dedicated memory is realized by (1) level control unit and (2) shift register arrays. To speed up the formation of bar-charts, the level control unit provides parallel control signals to the shift register arrays. Moreover, such an architecture can easily be updated when running any order operations are concerned. Our current design can handle at most 25 input samples with word-length of 8 bits, and the resultant IC shows that a 25-MHz clock rate can be achieved and the chip area is 0.69 x 0.56 cm2.
URI: http://hdl.handle.net/11536/2807
ISSN: 0167-9260
期刊: INTEGRATION-THE VLSI JOURNAL
Volume: 16
Issue: 1
起始頁: 91
結束頁: 103
顯示於類別:期刊論文