A pipeline structure for high-speed step-by-step RS decoding

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, TC	en_US
dc.contributor.author	Wei, CH	en_US
dc.contributor.author	Wei, SW	en_US
dc.date.accessioned	2014-12-08T15:41:19Z	-
dc.date.available	2014-12-08T15:41:19Z	-
dc.date.issued	2003-02-01	en_US
dc.identifier.issn	0916-8516	en_US
dc.identifier.uri	http://hdl.handle.net/11536/28104	-
dc.description.abstract	Based on a modified step-by-step decoding procedure, a high-speed pipelined Reed-Solomon decoder is presented. The decoder requires only the delay time of three 2-input XOR gates for decoding each coded symbol. The decoder can be operated in a bit rate of Gbits/sec order and thus suitable for the very high speed data transmission systems.	en_US
dc.language.iso	en_US	en_US
dc.subject	Reed-Solomon codes	en_US
dc.subject	step-by-step decoding	en_US
dc.subject	pipeline	en_US
dc.subject	high-speed transmission systems	en_US
dc.title	A pipeline structure for high-speed step-by-step RS decoding	en_US
dc.type	Letter	en_US
dc.identifier.journal	IEICE TRANSACTIONS ON COMMUNICATIONS	en_US
dc.citation.volume	E86B	en_US
dc.citation.issue	2	en_US
dc.citation.spage	847	en_US
dc.citation.epage	849	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000181032100044	-
dc.citation.woscount	1	-
顯示於類別：	期刊論文