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dc.contributor.authorLin, PCen_US
dc.contributor.authorPearn, WLen_US
dc.date.accessioned2014-12-08T15:41:39Z-
dc.date.available2014-12-08T15:41:39Z-
dc.date.issued2002-12-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://dx.doi.org/10.1016/S0026-2714(02)00103-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/28333-
dc.description.abstractProcess capability indices C-PU and C-PL have been widely used in the microelectronics manufacturing industry as capability measures for processes with one-sided specification limits. In this paper, the theory of statistical hypothesis testing is implemented for normal processes, using the uniformly minimum variance unbiased estimators of Cpu and CPL. Efficient SAS computer programs are provided to calculate the critical values and the p-values required for making decisions. Useful critical values for some commonly used capability requirements are tabulated. Based on the test a simple but practical step-by-step procedure is developed for in-plant applications. An example on the voltage level translator manufacturing process is given to illustrate how the proposed procedure may be applied to test whether the process meets the preset capability requirement. (C) 2002 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleTesting process capability for one-sided specification limit with application to the voltage level translatoren_US
dc.typeArticleen_US
dc.identifier.doi10.1016/S0026-2714(02)00103-8en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume42en_US
dc.citation.issue12en_US
dc.citation.spage1975en_US
dc.citation.epage1983en_US
dc.contributor.department工業工程與管理學系zh_TW
dc.contributor.departmentDepartment of Industrial Engineering and Managementen_US
dc.identifier.wosnumberWOS:000179954000018-
dc.citation.woscount12-
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