Precursor ISI-free frame synchronization for DMT VDSL system

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, ST	en_US
dc.contributor.author	Wei, CH	en_US
dc.date.accessioned	2014-12-08T15:42:09Z	-
dc.date.available	2014-12-08T15:42:09Z	-
dc.date.issued	2002-08-01	en_US
dc.identifier.issn	0916-8516	en_US
dc.identifier.uri	http://hdl.handle.net/11536/28634	-
dc.description.abstract	A new modified maximum likelihood (ML) algorithm for frame synchronization in discrete multitone VDSL transmission system is presented. Computer simulation results are included to show its improvement in Et/N-0 of each tone in the received data. This algorithm estimates the frame boundary at the initial transition edge rather than at the middle peak of a shortened twisted-pair channel response. The timing margin degradation caused by precursor intersymbol interference (ISI) can be reduced significantly, especially at the sub-channel loaded with more bits.	en_US
dc.language.iso	en_US	en_US
dc.subject	DMT	en_US
dc.subject	VDSL	en_US
dc.subject	frame synchronization	en_US
dc.subject	maximum likelihood estimation	en_US
dc.title	Precursor ISI-free frame synchronization for DMT VDSL system	en_US
dc.type	Article; Proceedings Paper	en_US
dc.identifier.journal	IEICE TRANSACTIONS ON COMMUNICATIONS	en_US
dc.citation.volume	E85B	en_US
dc.citation.issue	8	en_US
dc.citation.spage	1447	en_US
dc.citation.epage	1454	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000177439100005	-
顯示於類別：	會議論文