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dc.contributor.authorSu, JGen_US
dc.contributor.authorWong, SCen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorHuang, TYen_US
dc.date.accessioned2014-12-08T15:42:09Z-
dc.date.available2014-12-08T15:42:09Z-
dc.date.issued2002-08-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/S0038-1101(02)00022-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/28645-
dc.description.abstractA new gate capacitance extraction method from S-parameter measurements is proposed. The distributed nature of MOS transistor and the in-series substrate resistance and in-parallel gate conductance are taken into consideration in the gate capacitance extraction by using high-frequency S-parameter measurements. The error due to dissipation factor can be more effectively reduced by this method, compared to the conventional C-V measurements. Successful extraction of gate capacitance from test transistors with designed test pads has been demonstrated. (C) 2002 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleThe extraction of MOSFET gate capacitance from S-parameter measurementsen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/S0038-1101(02)00022-9en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume46en_US
dc.citation.issue8en_US
dc.citation.spage1163en_US
dc.citation.epage1167en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000177094400017-
dc.citation.woscount0-
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