標題: | The extraction of MOSFET gate capacitance from S-parameter measurements |
作者: | Su, JG Wong, SC Chang, CY Huang, TY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-八月-2002 |
摘要: | A new gate capacitance extraction method from S-parameter measurements is proposed. The distributed nature of MOS transistor and the in-series substrate resistance and in-parallel gate conductance are taken into consideration in the gate capacitance extraction by using high-frequency S-parameter measurements. The error due to dissipation factor can be more effectively reduced by this method, compared to the conventional C-V measurements. Successful extraction of gate capacitance from test transistors with designed test pads has been demonstrated. (C) 2002 Elsevier Science Ltd. All rights reserved. |
URI: | http://dx.doi.org/10.1016/S0038-1101(02)00022-9 http://hdl.handle.net/11536/28645 |
ISSN: | 0038-1101 |
DOI: | 10.1016/S0038-1101(02)00022-9 |
期刊: | SOLID-STATE ELECTRONICS |
Volume: | 46 |
Issue: | 8 |
起始頁: | 1163 |
結束頁: | 1167 |
顯示於類別: | 期刊論文 |