Integrated tungsten chemical mechanical polishing process characterization for via plug interconnection in ultralarge scale integrated circuits

Abstract

One integrated tungsten (W) chemical mechanical polishing (CMP) process characterization with wide production margin is developed for W plug application in sub-quarter micron technology. In this study, it is identified that donut-type function failure and reliability degradation on a designed application specific integrated circuit (ASIC) product vehicle result from an extra oxide layer atop the W plugs. W recess in via holes makes the plugs more vulnerable to oxide layer formation. CMP polish rate uniformity, layout dependence of via holes and queue-time (Q-time) control between WCMP and post-cleaning treatment are key parameters for preventing failure from interfacial oxide layer. Integrated optimization of WCMP process combined with W extrusion by a slight oxide polish immediately after WCMP is proposed to achieve a robust W plug process. Significant yield improvement from 45% to 82% in wafer edge region and 0% failure in three qualification lots in a product reliability test are demonstrated.