Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chen, SH | en_US |
dc.contributor.author | Chang, HC | en_US |
dc.contributor.author | Fu, DK | en_US |
dc.contributor.author | Chang, EY | en_US |
dc.contributor.author | Lai, YL | en_US |
dc.contributor.author | Cahng, L | en_US |
dc.date.accessioned | 2014-12-08T15:42:17Z | - |
dc.date.available | 2014-12-08T15:42:17Z | - |
dc.date.issued | 2002-07-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.41.4489 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/28703 | - |
dc.description.abstract | A novel submicron (<0.2 mum) T-shaped gate technology using a phase shift mask (PSM) technique is developed. The 8% half-tone PSM was selected for the definition of the isolated narrow space. Before lithography, a 2000 Angstrom SiN film was deposited on the wafer. After i-line PSM exposure and reactive ion etching (RIE) of the silicon nitride film, openings less than 0.2 mum wide were formed on the SiN film. To further reduce the dimensions of the openings, an additional 566 Angstrom nitride was then deposited on the wafer and etched back using RIE without any mask. An opening of 0.167 mum was formed on the wafer after the dry etching process. The wafer was then coated with another layer of photoresist to form a lift-off structure. The T-shaped gate with a length of 0.167 mum was obtained using this technique. The novel T-shaped gate technology is a high-throughput process for both silicon and compound semiconductor devices. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | T-shaped gate | en_US |
dc.subject | phase shift mask | en_US |
dc.subject | lithography | en_US |
dc.subject | field-effect transistors | en_US |
dc.subject | semiconductor devices | en_US |
dc.title | Novel I-line phase shift mask technique for submicron T-shaped gate formation | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1143/JJAP.41.4489 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
dc.citation.volume | 41 | en_US |
dc.citation.issue | 7A | en_US |
dc.citation.spage | 4489 | en_US |
dc.citation.epage | 4492 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000177512200014 | - |
dc.citation.woscount | 0 | - |
Appears in Collections: | Articles |
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