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dc.contributor.authorYu, Men_US
dc.contributor.authorLin, HCen_US
dc.contributor.authorChen, GHen_US
dc.contributor.authorHuang, TYen_US
dc.contributor.authorLei, TFen_US
dc.date.accessioned2014-12-08T15:42:25Z-
dc.date.available2014-12-08T15:42:25Z-
dc.date.issued2002-05-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.41.2815en_US
dc.identifier.urihttp://hdl.handle.net/11536/28807-
dc.description.abstractCharacteristics of polycrystalline silicon thin-film transistors (TFT) with source/drain extensions induced by a bottom sub-gate were explored, high on/off current ratio up to 10(7) could be achieved for both n- and p-channel devices. Nevertheless, the performance is significantly degraded by a marked increase of off-state leak-age current when the channel length is scaled below 1 mum. Moreover, a hump in the subthreshold current-voltage regime is observed. After careful analysis, it is found that the leakage current is strongly dependent on the field strength and is not a thermally activated process. A leakage path along the bottom interface of the poly-Si channel layer is proposed to explain these results.en_US
dc.language.isoen_USen_US
dc.subjectpoly-Sien_US
dc.subjectthin-film transistor (TFT)en_US
dc.subjectfield-induced drainen_US
dc.subjectleakageen_US
dc.subjectsub-gateen_US
dc.titleCharacteristics of polycrystalline silicon thin-film transistors with electrical source/drain extensions induced by a bottom sub-gateen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.41.2815en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume41en_US
dc.citation.issue5Aen_US
dc.citation.spage2815en_US
dc.citation.epage2820en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000176515700005-
dc.citation.woscount0-
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