HIGH-SPEED REED-SOLOMON DECODER FOR CORRECTING ERRORS AND ERASURES

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	WEI, CH	en_US
dc.contributor.author	CHEN, CC	en_US
dc.contributor.author	LIU, GS	en_US
dc.date.accessioned	2014-12-08T15:04:25Z	-
dc.date.available	2014-12-08T15:04:25Z	-
dc.date.issued	1993-08-01	en_US
dc.identifier.issn	0956-3776	en_US
dc.identifier.uri	http://hdl.handle.net/11536/2921	-
dc.description.abstract	A Reed-Solomon decoder for errors-and-erasures correction, based on a new algebraic decoding algorithm, is presented. This high-speed decoder requires only n clock cycles for decoding each received n-symbol block. A serial structure that requires very few multipliers and provides a general expression to calculate the coefficients of the erasure-locator polynomial is also presented. A (15, 11) RS decoder and its shortened version (7, 3) RS decoder are used as design examples to illustrate the operating procedure of the new decoding algorithm.	en_US
dc.language.iso	en_US	en_US
dc.subject	ERROR-CORRECTION CODING	en_US
dc.subject	REED-SOLOMON DECODER	en_US
dc.title	HIGH-SPEED REED-SOLOMON DECODER FOR CORRECTING ERRORS AND ERASURES	en_US
dc.type	Article	en_US
dc.identifier.journal	IEE PROCEEDINGS-I COMMUNICATIONS SPEECH AND VISION	en_US
dc.citation.volume	140	en_US
dc.citation.issue	4	en_US
dc.citation.spage	246	en_US
dc.citation.epage	254	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	電信研究中心	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.contributor.department	Center for Telecommunications Research	en_US
dc.identifier.wosnumber	WOS:A1993LY27500004	-
dc.citation.woscount	2	-
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