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dc.contributor.authorLiang, BSen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:43:20Z-
dc.date.available2014-12-08T15:43:20Z-
dc.date.issued2001-10-25en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttp://dx.doi.org/10.1049/el:20010901en_US
dc.identifier.urihttp://hdl.handle.net/11536/29335-
dc.description.abstractRedundant operations and stalls prevent a rendering pipeline from full-speed operation. To speed up the rendering pipeline, a triple queue structure is proposed to smooth the pipeline and to obtain benefit from deferred lighting. The results of cycle-accurate simulation show that the proposed structure can reduce rendering cycles to 52.9% in small size queues.en_US
dc.language.isoen_USen_US
dc.titleSpeed up of rendering pipeline by deferred lighting and triple queue structureen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/el:20010901en_US
dc.identifier.journalELECTRONICS LETTERSen_US
dc.citation.volume37en_US
dc.citation.issue22en_US
dc.citation.spage1332en_US
dc.citation.epage1333en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000171943100011-
dc.citation.woscount0-
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