標題: | Matching-based algorithm for FPGA channel segmentation design |
作者: | Chang, YW Lin, JM Wong, MDF 資訊工程學系 Department of Computer Science |
關鍵字: | detailed routing;interconnect;layout;physical design;routing |
公開日期: | 1-六月-2001 |
摘要: | Process technology advances have made multimillion gate field programmable gate arrays (FPGAs) a reality. A key issue that needs to be solved in order for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. Channel segmentation designs have been studied to some degree in much of the Literature; the previous methods are based on experimental studies, stochastic models, or analytical analysis, In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a problem of finding the optimal segmentation architecture for two input routing instances and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient multilevel matching-based algorithm for general channel segmentation designs. Experimental results show that our method significantly outperforms the previous work. For example, our method achieves average improvements of 18.2% and 8.9% in routability in comparison with other work. |
URI: | http://dx.doi.org/10.1109/43.924831 http://hdl.handle.net/11536/29611 |
ISSN: | 0278-0070 |
DOI: | 10.1109/43.924831 |
期刊: | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
Volume: | 20 |
Issue: | 6 |
起始頁: | 784 |
結束頁: | 791 |
顯示於類別: | 期刊論文 |