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dc.contributor.authorChang, YWen_US
dc.contributor.authorLin, JMen_US
dc.contributor.authorWong, MDFen_US
dc.date.accessioned2014-12-08T15:43:48Z-
dc.date.available2014-12-08T15:43:48Z-
dc.date.issued2001-06-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/43.924831en_US
dc.identifier.urihttp://hdl.handle.net/11536/29611-
dc.description.abstractProcess technology advances have made multimillion gate field programmable gate arrays (FPGAs) a reality. A key issue that needs to be solved in order for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. Channel segmentation designs have been studied to some degree in much of the Literature; the previous methods are based on experimental studies, stochastic models, or analytical analysis, In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a problem of finding the optimal segmentation architecture for two input routing instances and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient multilevel matching-based algorithm for general channel segmentation designs. Experimental results show that our method significantly outperforms the previous work. For example, our method achieves average improvements of 18.2% and 8.9% in routability in comparison with other work.en_US
dc.language.isoen_USen_US
dc.subjectdetailed routingen_US
dc.subjectinterconnecten_US
dc.subjectlayouten_US
dc.subjectphysical designen_US
dc.subjectroutingen_US
dc.titleMatching-based algorithm for FPGA channel segmentation designen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/43.924831en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume20en_US
dc.citation.issue6en_US
dc.citation.spage784en_US
dc.citation.epage791en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000168866600008-
dc.citation.woscount4-
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