A 60 mu A quiscent current, 250 mA CMOS low dropout regulator

Abstract

A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 mum CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which carl be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 muA and this LDO can provide a maximum output current of 250 mA. at an input voltage of 3.6 V. The active area of this LDO is 760 mum x 714 mum.