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dc.contributor.authorShih, PSen_US
dc.contributor.authorZan, HWen_US
dc.contributor.authorChang, TCen_US
dc.contributor.authorHuang, TYen_US
dc.contributor.authorChang, CYen_US
dc.date.accessioned2014-12-08T15:45:10Z-
dc.date.available2014-12-08T15:45:10Z-
dc.date.issued2000-07-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.39.3879en_US
dc.identifier.urihttp://hdl.handle.net/11536/30445-
dc.description.abstractN-channcl and p-channel polysilicon thin him transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.en_US
dc.language.isoen_USen_US
dc.subjectpoly-Si TFTen_US
dc.subjectdimensional effecten_US
dc.subjectdrain currenten_US
dc.subjectgrain-boundary trap densityen_US
dc.subjectkink effecten_US
dc.titleDimensional effects on the drain current of n- and p-channel polycrystalline silicon thin film transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.39.3879en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume39en_US
dc.citation.issue7Aen_US
dc.citation.spage3879en_US
dc.citation.epage3882en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000088909900008-
dc.citation.woscount2-
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