完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wong, SC | en_US |
dc.contributor.author | Lee, TGY | en_US |
dc.contributor.author | Ma, DJ | en_US |
dc.contributor.author | Chao, CJ | en_US |
dc.date.accessioned | 2014-12-08T15:45:20Z | - |
dc.date.available | 2014-12-08T15:45:20Z | - |
dc.date.issued | 2000-05-01 | en_US |
dc.identifier.issn | 0894-6507 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/66.843637 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30551 | - |
dc.description.abstract | We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 mu m and wire thickness down to 0.15 mu m. The model is useful for VLSI design and process optimization. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | closed-form models | en_US |
dc.subject | crossover capacitance | en_US |
dc.subject | multilevel interconnects | en_US |
dc.subject | VLSI circuits | en_US |
dc.title | An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.doi | 10.1109/66.843637 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | en_US |
dc.citation.volume | 13 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 219 | en_US |
dc.citation.epage | 227 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000087453300013 | - |
顯示於類別: | 會議論文 |