完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, LS | en_US |
dc.contributor.author | Lee, CL | en_US |
dc.date.accessioned | 2014-12-08T15:45:33Z | - |
dc.date.available | 2014-12-08T15:45:33Z | - |
dc.date.issued | 2000-03-16 | en_US |
dc.identifier.issn | 0013-5194 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1049/el:20000379 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30650 | - |
dc.description.abstract | It is demonstrated that Ar implantation can retard the epitaxial realignment of poly-Si/Si in an As- or P-doped n(+)-p poly-emitter diode during BF2 implantation. This is believed to be due to the gettering of As, P, and F by bubble-like defects created by the Ar implantation used to reduce the pile-up of these dopants at the poly-Si/Si interface. Consequently, there is less break-up of the interface oxide, resulting in a reduction in epitaxial realignment. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Reduction of epitaxial alignment in n(+)-p poly-Si emitter diode due to gettering of P and As by Ar implantation | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1049/el:20000379 | en_US |
dc.identifier.journal | ELECTRONICS LETTERS | en_US |
dc.citation.volume | 36 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 579 | en_US |
dc.citation.epage | 581 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000086381000066 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |