完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, M | en_US |
dc.contributor.author | Chang, CY | en_US |
dc.contributor.author | Huang, TY | en_US |
dc.contributor.author | Lin, ML | en_US |
dc.date.accessioned | 2014-12-08T15:46:05Z | - |
dc.date.available | 2014-12-08T15:46:05Z | - |
dc.date.issued | 1999-11-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30990 | - |
dc.description.abstract | A multilevel interconnect technology with an intra metal air gap has been developed to reduce the interconnect delay time for versatile. and quick turnaround-time foundry manufacturing. The air-gap method has been successfully applied to 0.25 mu m IC technology and shown to be effective in reducing the parasitic interconnect capacitance. Measurements of various ring oscillators confirm that the smallest delay time is indeed achieved with the air-gap method, compared with other methods using either conventional high-density-plasma (HDP) oxide or low-dielectric-constant spin-on-glass (SOG) as the gap-filling insulating materials. Moreover, the oscillator delay time is found to depend critically on not only the size of the air gap, but also the position of the air gap. Best results in terms of delay time reduction are obtained when the air-gap is positioned in the middle between the two metal lines, and extends both above and below the metal lines to effectively reduce the fringing capacitance. We have also measured the leakage current between adjacent metal lines and confirmed that our new metal intel connect structure with an air gap does not exhibit any appreciable leakage and appears to be suitable For high-performance foundry applications. Lastly, the polarization and thermal characteristics of the air-gap structure were compared with conventional gap-filling methods. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | air gap | en_US |
dc.subject | ring oscillator | en_US |
dc.subject | HDP | en_US |
dc.subject | SOG | en_US |
dc.subject | HSQ | en_US |
dc.title | A multilevel interconnect technology with intrametal air gap for high-performance 0.25-mu m-and-beyond devices manufacturing | en_US |
dc.type | Article | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
dc.citation.volume | 38 | en_US |
dc.citation.issue | 11 | en_US |
dc.citation.spage | 6240 | en_US |
dc.citation.epage | 6246 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000084041800014 | - |
dc.citation.woscount | 2 | - |
顯示於類別: | 期刊論文 |