完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ou, Shih-Hao | en_US |
dc.contributor.author | Cho, Yi | en_US |
dc.contributor.author | Lin, Tay-Jyi | en_US |
dc.contributor.author | Liu, Chih-Wei | en_US |
dc.date.accessioned | 2014-12-08T15:46:22Z | - |
dc.date.available | 2014-12-08T15:46:22Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-1-4244-2078-0 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31198 | - |
dc.description.abstract | A scalar (single-issue) processor executes one instruction at a time and its functional units (ALU, multiplier, and shifter, etc) are never concurrently exercised. Modem processors issue multiple instructions simultaneously (i.e. superscalar or VLIW) to improve their functional unit utilization but the cost is considerably high. In this paper, an alternative is described to activate multiple functional units concurrently by issuing a composite instruction on cascaded functional units. Besides, an automatic generator for application-specific composite functional units is presented. In our simulation with popular DSP applications, 35% increase on the operations per cycle ran be simply obtained with identical functional units. Moreover, our proposed approach saves up to 16.5% and 31.6% power on scalar and VLIW respectively for comparable performance. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Improving datapath utilization of programmable DSP with composite functional units | en_US |
dc.type | Article | en_US |
dc.identifier.journal | PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | en_US |
dc.citation.spage | 3438 | en_US |
dc.citation.epage | 3441 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000258532102318 | - |
顯示於類別: | 會議論文 |