完整後設資料紀錄
DC 欄位語言
dc.contributor.authorOu, Shih-Haoen_US
dc.contributor.authorCho, Yien_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorLiu, Chih-Weien_US
dc.date.accessioned2014-12-08T15:46:22Z-
dc.date.available2014-12-08T15:46:22Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2078-0en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/31198-
dc.description.abstractA scalar (single-issue) processor executes one instruction at a time and its functional units (ALU, multiplier, and shifter, etc) are never concurrently exercised. Modem processors issue multiple instructions simultaneously (i.e. superscalar or VLIW) to improve their functional unit utilization but the cost is considerably high. In this paper, an alternative is described to activate multiple functional units concurrently by issuing a composite instruction on cascaded functional units. Besides, an automatic generator for application-specific composite functional units is presented. In our simulation with popular DSP applications, 35% increase on the operations per cycle ran be simply obtained with identical functional units. Moreover, our proposed approach saves up to 16.5% and 31.6% power on scalar and VLIW respectively for comparable performance.en_US
dc.language.isoen_USen_US
dc.titleImproving datapath utilization of programmable DSP with composite functional unitsen_US
dc.typeArticleen_US
dc.identifier.journalPROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10en_US
dc.citation.spage3438en_US
dc.citation.epage3441en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000258532102318-
顯示於類別:會議論文