完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shiue, MT | en_US |
dc.contributor.author | Wang, CK | en_US |
dc.contributor.author | Way, WI | en_US |
dc.date.accessioned | 2014-12-08T15:47:14Z | - |
dc.date.available | 2014-12-08T15:47:14Z | - |
dc.date.issued | 1998-12-01 | en_US |
dc.identifier.issn | 0916-8516 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31690 | - |
dc.description.abstract | In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions [1], [2]. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are +/-6 kHz of carrier frequency offset, +/- 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | QAM | en_US |
dc.subject | VSB | en_US |
dc.subject | AGC | en_US |
dc.subject | carrier recovery | en_US |
dc.subject | timing recovery | en_US |
dc.subject | fractionally spaced blind equalizer and DFE | en_US |
dc.title | A VLSI architecture design for dual-mode QAM and VSB digital CATV transceiver | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.journal | IEICE TRANSACTIONS ON COMMUNICATIONS | en_US |
dc.citation.volume | E81B | en_US |
dc.citation.issue | 12 | en_US |
dc.citation.spage | 2351 | en_US |
dc.citation.epage | 2356 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000077770300014 | - |
顯示於類別: | 會議論文 |