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dc.contributor.authorChen, Yu-Tingen_US
dc.contributor.authorChen, Kun-Mingen_US
dc.contributor.authorLiao, Wen-Shiangen_US
dc.contributor.authorHuang, Guo-Weien_US
dc.contributor.authorHuang, Fon-Shanen_US
dc.date.accessioned2014-12-08T15:47:37Z-
dc.date.available2014-12-08T15:47:37Z-
dc.date.issued2010-12-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2010.2073438en_US
dc.identifier.urihttp://hdl.handle.net/11536/31877-
dc.description.abstractThe 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiN(x) stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability.en_US
dc.language.isoen_USen_US
dc.titleImpact of Highly Compressive Interlayer-Dielectric-SiN(x) Stressing Layer on 1/f Noise and Reliability of SiGe-Channel pMOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2010.2073438en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume31en_US
dc.citation.issue12en_US
dc.citation.spage1368en_US
dc.citation.epage1370en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
Appears in Collections:Articles