完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Yu-Ting | en_US |
dc.contributor.author | Chen, Kun-Ming | en_US |
dc.contributor.author | Liao, Wen-Shiang | en_US |
dc.contributor.author | Huang, Guo-Wei | en_US |
dc.contributor.author | Huang, Fon-Shan | en_US |
dc.date.accessioned | 2014-12-08T15:47:37Z | - |
dc.date.available | 2014-12-08T15:47:37Z | - |
dc.date.issued | 2010-12-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2010.2073438 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31877 | - |
dc.description.abstract | The 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiN(x) stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Impact of Highly Compressive Interlayer-Dielectric-SiN(x) Stressing Layer on 1/f Noise and Reliability of SiGe-Channel pMOSFETs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2010.2073438 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 31 | en_US |
dc.citation.issue | 12 | en_US |
dc.citation.spage | 1368 | en_US |
dc.citation.epage | 1370 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
顯示於類別: | 期刊論文 |