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dc.contributor.authorHsieh, E. R.en_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorLin, Y. H.en_US
dc.contributor.authorTsai, C. H.en_US
dc.contributor.authorLiu, P. W.en_US
dc.contributor.authorTsai, C. T.en_US
dc.contributor.authorMa, G. H.en_US
dc.contributor.authorChien, S. C.en_US
dc.contributor.authorSun, S. W.en_US
dc.date.accessioned2014-12-08T15:48:21Z-
dc.date.available2014-12-08T15:48:21Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2071-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/32209-
dc.description.abstractIn this work, for the first time, an abnormal leakage current has been observed in MOSFET with 50nm channel length and beyond. This effect shows that, in an ultra-short channel MOSFET, sub-threshold swing (SS) and I(off) are decreased for back-biased nMOSFET and pMOSFET. This effect is attributed to the BJT-induced current from the source to the drain. An experimental approach has been used to verify the existence of this BJT current component. As a consequence, this BIT current can be reduced with appropriate control of the S/D-to-substrate junction. As an application of the approach to advanced embedded-SiC MOSFET with various splits, it was found that a higher band-offset of S/D-to-substrate junction will give rise to a larger the BJT ballistic transport current. This provides us important information on reducing the leakage current for advanced CMOS with 50nm and beyond.en_US
dc.language.isoen_USen_US
dc.titleNew Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyonden_US
dc.typeArticleen_US
dc.identifier.journal2008 IEEE SILICON NANOELECTRONICS WORKSHOPen_US
dc.citation.spage89en_US
dc.citation.epage90en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000279102800046-
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