Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wu, Yu-Ze | en_US |
dc.contributor.author | Chao, Mango C. -T. | en_US |
dc.date.accessioned | 2014-12-08T15:48:34Z | - |
dc.date.available | 2014-12-08T15:48:34Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-0-7695-3123-6 | en_US |
dc.identifier.issn | 1093-0167 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/32309 | - |
dc.identifier.uri | http://dx.doi.org/10.1109/VTS.2008.16 | en_US |
dc.description.abstract | This paper proposes a scan-cell reordering scheme, named ROBPR, to reduce the signal transitions during test mode while preserving the don't-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scheme utilizes both response correlation and pattern correlation to simultaneously minimize scan-out and scan-in transitions. A series of experiments demonstrate the effectiveness and superiority of the proposed scheme on reducing total scan-shift transitions. The trade-off between our power-driven scan-cell reordering and a routing-driven scan-cell reordering is discussed based on experiments as well. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Scan-chain reordering for minimizing scan-shift power based on non-specified test cubes | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/VTS.2008.16 | en_US |
dc.identifier.journal | 26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | en_US |
dc.citation.spage | 147 | en_US |
dc.citation.epage | 154 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000256250900021 | - |
Appears in Collections: | Conferences Paper |
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