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dc.contributor.authorWu, Yu-Zeen_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.date.accessioned2014-12-08T15:48:34Z-
dc.date.available2014-12-08T15:48:34Z-
dc.date.issued2008en_US
dc.identifier.isbn978-0-7695-3123-6en_US
dc.identifier.issn1093-0167en_US
dc.identifier.urihttp://hdl.handle.net/11536/32309-
dc.identifier.urihttp://dx.doi.org/10.1109/VTS.2008.16en_US
dc.description.abstractThis paper proposes a scan-cell reordering scheme, named ROBPR, to reduce the signal transitions during test mode while preserving the don't-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scheme utilizes both response correlation and pattern correlation to simultaneously minimize scan-out and scan-in transitions. A series of experiments demonstrate the effectiveness and superiority of the proposed scheme on reducing total scan-shift transitions. The trade-off between our power-driven scan-cell reordering and a routing-driven scan-cell reordering is discussed based on experiments as well.en_US
dc.language.isoen_USen_US
dc.titleScan-chain reordering for minimizing scan-shift power based on non-specified test cubesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/VTS.2008.16en_US
dc.identifier.journal26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGSen_US
dc.citation.spage147en_US
dc.citation.epage154en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000256250900021-
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