完整後設資料紀錄
DC 欄位語言
dc.contributor.authorJUANG, MHen_US
dc.contributor.authorCHENG, HCen_US
dc.date.accessioned2014-12-08T15:04:46Z-
dc.date.available2014-12-08T15:04:46Z-
dc.date.issued1992-10-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://hdl.handle.net/11536/3271-
dc.description.abstractHigh-quality silicided shallow n+p junctions have been fabricated by P+ implantation into thin Ti films on Si substrates and by moderate implant conditions as well as subsequent high-temperature rapid thermal annealing (RTA) followed by low-temperature conventional furnace annealing (CFA). RTA minimizes the diffusion of knock-on Ti but greatly reduces the drive-in efficiency because of its short annealing time. Driving the dopants out of silicides via long-time annealing was associated with the crystallinity of silicides. The junctions formed by this scheme with respect to various implant and anneal conditions have been characterized. In addition, the distribution profile of Ti penetration was correlated with the effective generation life time obtained from the reverse I-V curves.en_US
dc.language.isoen_USen_US
dc.titleCHARACTERIZATION OF SILICIDED SHALLOW N+P JUNCTIONS FORMED BY P+ IMPLANTATION INTO THIN TI FILMS ON SI SUBSTRATESen_US
dc.typeArticleen_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume35en_US
dc.citation.issue10en_US
dc.citation.spage1535en_US
dc.citation.epage1542en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1992JP71900025-
dc.citation.woscount4-
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