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dc.contributor.authorHuang, Zhe-Yangen_US
dc.contributor.authorHuang, Che-Chengen_US
dc.contributor.authorChen, Chun-Chiehen_US
dc.contributor.authorHung, Chung-Chihen_US
dc.contributor.authorJou, Christina F.en_US
dc.date.accessioned2014-12-08T15:04:50Z-
dc.date.available2014-12-08T15:04:50Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-1616-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/3353-
dc.description.abstractIn this paper, a CMOS low-noise amplifier (LNA) is designed for ultra-wideband (UWB) wireless receiver system. The design consists of a wideband input impedance matching network, two stage cascode amplifiers with shunt-peaking load and an output buffer for measurement purpose. It was fabricated in UMC 0.18um standard RF CMOS process. The LNA provides 14.1dB maximum power gain between 2.3GHz-8.0GH while consuming 18.6mW (including buffer) through a 1.8V supply. Over the 3.1GHz-8.0GHz frequency band, a minimum noise figure is 2.0dB. The input return loss is lower than - 7.1dB in the entire bandwidth has also been achieved.en_US
dc.language.isoen_USen_US
dc.subjectRFICen_US
dc.subjectUWBen_US
dc.subjectultra-widebanden_US
dc.subjectLNAen_US
dc.subjectlow-noise amplifier and shunt-peakingen_US
dc.titleCMOS low-noise amplifier with shunt-peaking load for group 1 similar to 3 MB-OFDM ultra-wideband wireless receiveren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAMen_US
dc.citation.spage251en_US
dc.citation.epage254en_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.identifier.wosnumberWOS:000256565800062-
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