沉積後電漿處理與退火製程對二氧化鉿熱穩定性之影響

Abstract

隨著CMOS 技術急速的微縮到奈米技術點，傳統閘極介電層二氧化矽層將 達到其物理與電性限制。主要的問題是的量子效應引發無法接受的大量的□子直 接穿隧電流(Direct Tunneling Current)穿隧超薄二氧化矽層。為了可以有效的抑制此漏電流，高介電常數的閘極介電層材料會被使用來取代傳統的二氧化矽層而可以維持在相同的等效電性氧化層厚度(EOT)下增加實際介電層膜的厚度。 隨著金氧半場效電晶體的微縮，二氧化矽當作閘極介電層將面臨到物理限制。當互補式金氧半場效電晶體的閘極通道長度微縮到100奈米以下時，閘極介電層的有效電性厚度將縮小至1.2奈米以下，以二氧化矽當作氧化層將會面臨到很多的挑戰，影響最嚴重的就是超薄厚度之二氧化矽絕緣膜其直接穿遂電流將大到無可忍受的程度，因此需要高介電係數材料來取代二氧化矽作為閘極氧化層。高介電係數氧化層可以擁有較厚的物理厚度而維持相同的等效氧化層厚度來抑制穿遂電流的形成。其中以金屬鉿為主的材料被認為是目前最有可能來取代二氧化矽。本實驗以鋁-鈦-HfO2-矽之MIS結構為分析元件。首先，我們利用金屬有機物化學氣相沉積方法分別在矽晶片上沉積HfO2，然後進行不同溫度的沉積後退火步驟，找出最適當的退火溫度。接著再分別進行表面電漿處理以及電漿後的退火步驟。接著，我們進行600度60秒的高溫快速熱退火。最後，我們進行800~900度30秒的高溫處理，我們利用量測C-V和I-V曲線去探討薄膜的基本特性。另外藉由磁滯效應、SILC特性、CVS測試和變溫測試來討論經過電漿處理和沒有經過電漿處理元件的可靠度分析。我們可以發現經過電漿處理的試片可以承受較高的溫度卻不會降低原本的電容值。這是因為電漿源中的氮原子可以抑制介電層和矽之間的氧化層成長。

As CMOS devices are scaled aggressively into nanometer regime, SiO2 gate dielectric is approaching its physical and electrical limits. The primary issue is the intolerably huge leakage current caused by the direct tunneling of carriers through the ultrathin oxide. To substantially suppress the leakage current, high-k materials are recently employed by exploiting the increased physical thickness at the same equivalent oxide thickness (EOT). The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO2 as the gate insulator. When the gate oxide thickness scales down below 1.2 nm for 100 nm-node CMOS technology and beyond and the SiO2 will face severe challenges such as the direct-tunneling current. Therefore, high dielectric constant gate oxides with large physical thickness while identical equivalent oxide thickness (EOT) have been used to replace SiO2 in order to reduce gate leakage current. HfO2 dielectric is a most suitable material for future MOSFET gate oxide applications. In this study, we analysis the Al/ Ti/ HfO2 /Si MOS structure. First, we deposited HfO2 and on Si wafers individually by metal-organic CVD (MOCVD) system. Then, the films received different post-deposition-annealing temperature. After PDA, we had additional plasma treatment and post-nitridation annealing 600℃ 60 sec (PNA). Next, we treated the films with high temperature 800℃, 850℃ and 900℃ 30 sec. The electrical characteristics of the film were discussed by C-V and I-V curves. The reliability of the film with nitridation or not were discussed by hystersis effect, SILC( Stress Induce Leakage Current), CVS(Constant Voltage Stress) test and measure at different temperature. We could find that that the film with nitridation could sustain high thermal stress, and its capacitance did not decrease. It might be that nitrogen could suppress the formation of interfacial layer between the high-k/Si interface.