田口式直交表實驗法於積體電路設計

Abstract

此篇論文將運用田口方法運用簡單的直交表與簡潔的因子反應分析，以最少量的實驗數據進行分析，可有效提升靜電放電防護能力。簡而言之，使用較少量的實驗組合得到最佳資訊。我們所知，隨著半導體製程技術的進步，積體電路的元件尺寸也隨之縮小。然而，靜電對於積體電路晶片的傷害並沒有隨之消失，反而導致晶片對於靜電放電的免疫能力下降。為了增加晶片之靜電放電防護，許多解決之道相繼被提出。現今靜電放電(ESD)防護面臨棘手的研究問題主要在於，測試變因複雜、量測效率下降。在防護設計與實驗階段，靜電防護測試晶片眾多的腳位及佈局面積，都影響到研究的量測時間及研發成本。因此，這篇論文著重於田口式直交實驗法在靜電放電(ESD)概念介紹。

This thesis proposes a Taguchi’s orthogonal arrays concept of which the Electrostatic Discharge (ESD) protection quality can be effectively improved by using a simple orthogonal array experimental design as well as a simplified factor response analysis and referring to small quantity of experimental statistics for further analysis. In other words, using few experimental combinations can lead to the acquisition of useful information. As we know, the state of the art manufacture technology of integrated circuits leads to considerable device scale-down. However, the Electrostatic Discharge damage does not fade out while the device size is shrinking. On the other hand, the smaller IC size is, the lower ESD robustness it has. To avoid ESD damage, many of solutions to ESD protection have been proposed. One of the thorniest problems research face is testing factor complex and efficiency decline in the present day. The ESD protection chip with a lot of pins and layout area affects the testing time and cost. It’s an important issue for designer to understand ESD phenomena in increase robust quality design, decrease testing time and cost. Thus, the importance of this thesis is the introduction of the Taguchi’s orthogonal arrays concept on ESD.