非晶矽薄膜電晶體在汲極直流或交流操作下的劣化行為研究

Abstract

非晶矽薄膜電晶體(a-Si:H TFTs)在閘極直流或交流電壓操作下的劣化機制已被廣泛的討論；然而在更先進的應用中，非晶矽薄膜電晶體不再只是扮演畫素開關的角色，而是逐漸朝向驅動元件的方向發展，和傳統應用不同的地方在於非晶矽薄膜電晶體在驅動電路中會同時受到閘極和汲極信號的作用；因此，其在閘極和汲極信號下的劣化行為值得被深入研究。 在本論文中，非晶矽薄膜電晶體在閘極偏壓(On region)的汲極直流操作以及在閘極接地(Off region)的汲極直流操作下的劣化行為被提出來探討；另外，將汲極直流信號改為具有不同峰值電壓、頻率、開啟比率的交流信號操作下的劣化行為亦同時被提出來做深入的研究。 關於直流操作實驗的結果顯示：在閘極偏壓的汲極直流操作下，劣化會隨著汲極電壓的增加而減輕；這是肇因於當汲極電壓增加時電晶體通道內的載子會因閘極和汲極間相對電壓的降低而隨之減少，因而造成劣化的減輕；然而當閘極接地的汲極直流操作下，趨勢卻是相反；在此操作情形下隨著汲極電壓的增加，劣化會顯得更為嚴重；同時發現在閘極接地的汲極直流操作下，電晶體內的劣化位置將呈現不對稱分布，此現象可透過正向和反向汲極電流的測量而觀察到。 汲極交流信號操作的實驗結果顯示：劣化的情形類似於汲極直流的操作，而在頻率相關的實驗結果中，在閘極偏壓的汲極交流操作下，電晶體劣化和交流信號的頻率無明顯相關，主要是因為通道內的載子為具有快速累積能力的電子；相對於此，在閘極接地的汲極交流操作下，劣化則和頻率有明顯的相關；除了交流頻率的實驗，在汲極交流信號開啟比率的實驗結果中，發現在特定頻率下無論閘極偏壓的施加與否，汲極交流信號的有效操作時間將會影響整個劣化的行為。 在完成所有實驗後，根據實驗結果，我們在論文中提出了一個具有線性組合的劣化模型；藉由此模型的運用，我們可以預估施加不同電壓準位、不同頻率，不同開啟比率的汲極交流信號，經過任何操作時間後的臨界電壓變化；而量測的結果顯示此模型具有相當高的可靠性，可用以預測非晶矽薄膜電晶體電路在同時受到閘極和汲極信號操作下的可靠度以及電路的壽命。

The degradation mechanisms of a-Si:H TFTs under gate DC (direct current) and AC (alternating current) stress had been widely discussed. However, with the extending of advanced applications, a-Si:H TFTs no longer play the roles as switch elements but driving devices. Unlike traditional application, TFTs in driving circuits are subjected to signals in both gate and drain terminals. Therefore, the degradation behavior under both drain and gate stress should be understood in detail. In this thesis, the degradation of a-Si:H TFTs under drain DC stress in both on (with gate voltage bias) and off (with gate grounded) regions has been investigated. In addition, the degradation under on and off region drain AC stress with different peak levels, frequencies and duty ratios is also studied. It is found that the degradation decreases as drain voltage level increases for on region drain DC stress. The carriers induced in the channel are reduced with increasing drain bias, which result in the decreasing of degradation. But for off region drain DC stress, we have observed the contrary results. The degradation behavior is similar to negative gate DC stress and would become serious as drain voltage increased. Also, it is found that the degradation in TFTs under off region drain stress is not symmetric. Different degradation amplitude between forward measurement and reverse measurement is observed. For drain AC stress, the degradation shows similar behavior as drain DC stress. It is found that the degradation has no obvious frequency dependence in on region drain AC stress because of the carriers are electrons which have fast accumulation ability. But it shows apparent frequency dependence when performing off region drain AC stress. For the duty ratio experiment under low frequency, it is found that the effective stress time will dominate in both on and off region drain AC stress. Furthermore, base on the experiment result, a linear combination model has been contributed in this thesis. By using this model, we can estimate the threshold voltage shift under drain AC stress of different voltage levels, frequencies and duty ratios after any stress time. With satisfied agreement of our real measured data, this model has been proved to be very useful for the design of advanced a-Si:H circuits that suffers gate and drain stress and would be suitable for evaluating their reliability.