雙閘極奈米線非揮發性記憶元件之研製與分析

Abstract

在本篇論文中，我們成功地利用邊襯蝕刻技術(sidewall spacer over-etching technique)製作出具有奈米線通道的薄膜記憶體結構。同時，我們也利用雙閘極結構，對於元件的基本電性以及寫入/抹除特性做詳盡的研究與分析。 由於奈米線與雙閘極結構具有高表面體積比(high surface-to-volume ratio)能有效提升閘極控制能力，且在降低短通道效應與次臨界擺幅(subthreshold swing)方面都有顯著的改善。在此奈米線結構中，氮化矽覆蓋層被證實能有效降低漏電流。另外，利用雙閘極結構，我們提出一種新的「可調變式寫入/抹除速度」的方法。在一最佳化偏壓條件下，不需改變元件材料或介電層厚度就能有效提升寫入/抹除速度。然而，可靠度的表現需要有效地被改善，例如在通道形狀、製程步驟或是介電層材料方面著手，才能在實際上有所應用。

In this thesis, nanowire SONOS devices were fabricated by use of sidewall spacer over-etching technique. Furthermore, the fabricated devices were equipped with double-gated configuration. Impacts of the structural features on basic transfer characteristics and programming/erasing (P/E) characteristics were investigated and discussed in detail. It was found that the nanowire channel and double-gated structures were capable of enhancing the gate controllability by taking advantage of high surface-to-volume ratio, and led to improved characteristics such as reduced short channel effects and better subthreshold swing. To reduce the off-state leakage, the adoption of a silicon nitride (SiN) hardmask layer was demonstrated. Besides, a new concept of modulating the P/E speed with the double-gated operation was also proposed in this thesis. It was shown that the P/E speed could be enhanced with an optimized biasing condition. Nevertheless, the reliability characteristics of the NW SONOS devices remain an issue for practical application. Further optimizations in NW shape, process condition, as well as the ONO structure are needed.