具有真空間隙之T型閘極低溫多晶矽薄膜電晶體之性能與可靠度之研究

Abstract

系統面版 (System on Panel, SOP) 應用為複晶矽薄膜電晶體技術發展的理想目標，除高性能與高可靠度的要求外，必須兼具成本考量。傳統之汲極工程雖可降低漏電流與提升可靠度，卻伴隨著驅動電流的衰減，已有一些技術提出可以改善這些現象，然而卻大幅提昇元件製作的成本。在這篇論文裡，我們將提出一種低製作成本的元件結構，利用該結構來增進複晶矽薄膜電晶體的電特性與可靠度。 首先，我們藉由模擬分析證實具有真空間隙之T型閘極結構能有效舒緩複晶矽薄膜電晶體汲極端的大電場及碰撞游離 (Impact ionization) 的現象，尤其在具較薄的閘極氧化層之元件中，此一效應越趨明顯。 實驗結果顯示具有真空間隙之T型閘極複晶矽薄膜電晶體擁有極佳的開關特性比，由於T型閘極複晶矽薄膜電晶體中的偏移區域(Offset)有次閘極(Sub-Gate)的協助導通，我們觀察到所提出的新穎結構在大幅度抑制元件漏電流的同時仍維持驅動電流的大小。此外具真空間隙之T型閘極結構亦成功改善因汲極端大電場所造成的扭結效應 (Kink effect)。 接著，藉由電特性的對稱性分析，我們證實所提出的T型閘極製作方式為自我對準(Self-aligned)製程。另外，我們也觀察到所提出的新穎結構能降低汲極端的垂直電場進而增加閘極電壓的操作範圍。 最後，我們也研究具有真空間隙之T型閘極複晶矽薄膜電晶體在熱載子應力測試下的可靠度。利用典型的熱載子劣化分析，證實所提出的新穎結構在可靠度測試後的劣化程度較傳統元件的輕微很多，這也驗證了所提出的元件確實具有可實際應用的價值。

System on panel (SOP) is the admirable goal of polycrystalline silicon (poly-Si) thin film transistors (TFTs) applications. For such applications, poly-Si TFTs must have high performance and high reliability with low production cost. Conventional structure of drain engineering can reduce the leakage current and improve the reliability. Nevertheless, the driving capability is also decayed at the same time. In previous works, some techniques were proposed to modify the predicament; however the fabrication cost is remarkably increased due to their additional lithography step or complex process. In this thesis, a novel drain-field-relief structure with a simple fabrication process was introduced to improve the performance and reliability of poly-Si TFTs. In the beginning, device simulation was carried out to verify the effects of vacuum gap on the electric field near the drain junction. The electric field and impact ionization rate were significantly suppressed in those T-Gate TFTs, especially with thinner gate insulator. Experimental results revealed that T-Gate TFTs had excellent on/off current ratio exceeding 109. Due to the sub-gate coupling to the offset region, it was observed that the leakage current is dramatically suppressed while as the magnitude of driving current almost keeps the same level as that for the conventional one. Furthermore, kink effect was also reduced by T-Gate structure. By the symmetry analysis of electrical characteristics, the self-alignment property of T-shaped-gate formation was verified. Besides, the improvement of oxide breakdown characteristics was observed to enlarge the operation range of gate bias. Finally, we also examine the reliability of the proposed devices with typical hot carrier stress. The conventional devices exhibit serious degradation such as decayed transconductance, worse drain induced barrier lowering (DIBL), and larger threshold voltage shift. The proposed devices, have much superior immunity to the hot carrier degradation as compared with the conventional ones under the same stress condition. As a consequence, the proposed T-Gate TFTs have not only low-cost fabrication process but also excellent performance and better reliability.