以雜號干擾最小化為目標並符合延遲條件之技術映射

Abstract

在現今的超大型積體電路的設計中，隨之成長的雜訊干擾現象而造成晶片失敗或良率降低，已變成很重要的課題。在本篇論文中，我們提出了在技術映射階段，就可減少雜訊干擾並符合延遲條件的演算法。在技術映射的比對階段，此演算法採用了動態規劃架構，並且為了能機率性地估量通道的佔用，所以決定了所有配對的輸入端的繞線，這些繞線將被儲存成虛擬的繞線地圖，以期在覆蓋階段能夠計算雜訊干擾；而在覆蓋階段，將會選擇雜訊干擾最小且符合延遲條件的配對來取代延遲最小的配對。根據以聯電90奈米製程為技術資料庫而進行對標準測試電路的模擬實驗中，在對傳統的延遲最佳化之技術映射比較下，顯示了我們的演算法可以有效的減少雜訊干擾，改進平均值達到百分之二十五。

In today's VLSI designs, the growing of crosstalk effects causing chips to fail or suffer from low yields has become the important issue. In this thesis, we propose a technology mapping algorithm that can reduce the crosstalk noise while meeting delay constraints. The algorithm employing a dynamic programming framework in the matching phase determines the routing of fanin nets for all the matches to estimate the track utilization in probability. These routings are stored as virtual routing maps to compute the crosstalk noise during the covering phase, which will select the crosstalk-optimal solutions satisfying the delay constraints rather than the delay-optimal ones by slack caculation. Experimental results on benchmark circuits in UMC 90 nm process show that the algorithm is effective to improve the crosstalk by 25\% on average, as compared to the conventional delay-oriented technology mapping.