低密度同位元檢查碼之解碼演算法改進及適用於IEEE 802.3an之高速解碼器設計

Abstract

在本論文中，我們提出了一個有效改善Bit-Flipping(BF) 演算法錯誤更正效能及降低其解碼迴圈數的低密度同位元檢查碼解碼演算法，並將此演算法實作在IEEE 802.3an標準中。由於BF演算法不需要額外的記憶體來儲存在每個解碼迴圈所產生的新訊息值，因此硬體面積會相較於Belief-Propagation (BP)-based 的解碼器來的小許多。在實作過程中，我們提出了一個特別的設計，使在限定的週期數中，從2048個訊息裡找出前8大的數值的演算法及其硬體架構，稱之為動態層級位移器。在解碼器的硬體架構上，也將所使用的解碼演算法作一些順序上的調整及適當的化簡，使其能夠運作在高速環境下，達到規格所要求的高傳輸速率(bps)，也可達到100% 的硬體使用率和即時處理的目的。採用UMC 90nm製程合成，在頻率為500MHz下，最高可達到傳輸速率16.25Gbps，其晶片面積為1.42M個邏輯閘，平均功率消耗為368mW。

In this thesis, we propose a LDPC decoding algorithm which efficiently improves the error correcting performance and reduces the decoding iteration number for Bit-Flipping (BF) algorithms. Then, we implement the proposed algorithm for IEEE 802.3an standard. Since the BF algorithms do not need any additional memory to store the updated message in each iteration, the hardware area will be much smaller the Belief-Propagation (BP)-based decoder. During implementation, we propose a special hardware architecture, named dynamic level shifter, to find out the largest eight values from the 2048 message in a given clock cycles. For the architecture of the proposed decoder, we also adjust the decoding steps of the adopted algorithm and make some proper simplifications in order to operate under high speed environment and achieve the high throughput requirement defined in the IEEE 802.3an standard. It can also achieve the 100% hardware utilization and real-time processing. After synthesis in UMC 90nm process, the maximum throughput is about 16.25Gbps under the 500MHz clock frequency, the gate count of the chip area is 1.42M and the average power dissipation is 368mW.