嵌入式動態隨機存取記憶體測試方法

Abstract

由於嵌入式動態隨機存取記憶體以靜態隨機存取記憶體界面(所謂的1T-SRAM)所構成，因此嵌入式動態隨機存取記憶體測試混合了動態隨機存取記憶體與靜態隨機存取記憶體的測試，在這篇論文中，我們首先針對嵌入式動態隨機存取記憶體測試提出了測試演算法。然後，對於電閘電晶體漏電機制的理論分析也同樣被提供；以此為基礎，我們可以在較高的溫度測試嵌入式動態隨機存取記憶體，並減少整體測試時間與維持同樣的資料維持時間錯誤涵蓋率。實驗的結果是從一批16Mb的嵌入式動態隨機存取記憶體晶片收集得到的。

The embedded-DRAM testing mixes up the techniques used for DRAM testing and SRAM testing since an embedded-DRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this thesis, we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. The experimental results are collected based on 1-lot wafers with an 16Mb embedded DRAM core.