應用雙響應曲面方法於強健晶圓參數設計

Abstract

半導體廠每批產品的正確率被稱為良率；提高良率為製程品質管理的重要課題之一，本論文的目標在於提高晶圓良率。要提高產品良率，就必須找出影響良率的參數並加以調整。由於製程技術，我們了解晶圓允收參數值的變化代表良率的高低，而影響此參數變化的不僅有控制參數(critical dimensions)，還有雜訊參數。如何有效的調整控制參數並且降低雜訊參數所造成的影響，是我們所面臨的最大問題。於本論文中，我們利用雙響應曲面方法來描述因控制參數及雜訊參數的影響下，晶圓允收參數值的變化。接著利用強健參數設計方法，設計出最佳的控制參數值；使得晶圓允收參數能夠達到我們所預期的目標且使經由雜訊參數所造成的影響能夠降至最低。

The accuracy of products in every lot called yield. To improve the yield is important for the quality management of wafer fabrication. The goal of this thesis is to advance the yield. If you want to improve the yield, you have to find the parameters which affect the yield most, then, adjust it. Due to the technique of wafer fabrication, we know the change of wafer electrical test (WET) factors present the quality of the yield. There are not only control factors, critical dimensions, but also noise factors which can affect WET factors. How we can adjust control factors efficiently and minimize the effect of noise factors is the critical problem in the study. In the thesis, we use the dual responses model to describe the relationship of critical dimension, noise factors, and WET factors. Then, we use the robust parameter design method to devise the optimum combination of critical dimensions such that WET factors can be satisfied with prescribed specifications and the effect occurred by noise factors is minimum.