交換電容式積分器之運算放大器增益補償的設計

Abstract

在類比系統中, 切換電容積分器為具有重要功能的電路。切換電容積分器包含一運算放大器。 運算放大器的非理想特性, 例如有限增益, 有限頻寬以及輸入偏移將會降低積分器的效能。 舉例來說,運算放大器之有限增益將會使離散時間積分器的極點偏離理想位置z=1, 造成有限的直流增益及相位誤差。 這個影響顯著地降低了三角積分 調變器之MASH架構的性能, 因為對雜訊修整濾波器而言直流值上不再有一零點。 一直接的方法為設計運算放大器有非常大的增益, 但是以現在的技術要達到高增益是非常複雜以及幾乎不可能。 在本論文中我們專注於有限增益運算放大器對切換電容積分器的影響, 並且設計一可以降低因運算放大器有限增益所造成在積分器之轉移函數上誤差的新型切換電容積分器。 因此, 這經過設計的積分器可以等效增加運算放大器的增益, 以及改善其在應用上的效能。 此新架構是以相關雙取樣的方法及利用回授運算放大器被提出。 我們首先推導其轉移函數並使用MATLAB計算因運算放大器有限增益造成的誤差。 其性能將與現有的電路做比較。 接著, 我們使用TSMC0.35微米互補式金氧半的製程來設計, 以及HSPICE來模擬電路在數個頻率之頻率響應。 預先模擬與佈局後模擬的結果接近相同, 並且與原始設計規格相符。 最後畫出電路佈局, 晶片大小大約是240×235um^2。

The Switched Capacitor(SC) integrator is an important functional circuit block in the analog systems. A SC integrator contains an operational amplifier. The non-idealities of the operational amplifier, such as the finite gain, the finite bandwidth, and the input offset will degrade the performance of the integrator. For example, the finite-gain of the operational amplifier will make the pole of discrete-time integrator deviate from the ideal position $z=1$ yielding a DC finite gain and phase error in the SC integrator. This effect degrades significantly the performance of delta sigma modulators via the MASH structure, because the noise-shaping filter has no longer a zero at DC. One direct approach is to design an op-amp with extremely high gain, but it is complicated and nearly impossible via the present technology. In this thesis, we focus on the effect of finite-gain op-amp in SC integrators, and design a new SC integrator circuit which can reduce the error in the integrator transfer characteristic due to the finite-gain of the op-amp. Hence, the designed integrator enhances equivalently the op-amp finite gain, and improves the performance in applications. The new topology is proposed using the feedback op-amp and the correlated double sampling (CDS) technique. We first derive the transfer function and use MATLAB to evaluate the errors arisen from the effect of finite-gain in op-amp. The performances of proposed circuit and other existing circuits are compared. Then, we design the circuit using TSMC 0.35mu CMOS technology, and simulate the circuit frequency responses at several frequencies via HSPICE. The pre-sim or post-sim simulation results are approximately identical, and conform to the original design specifications. Finally, the layout is drawn and the chip size is about 240×235um^2.