應用於Millimeter Wave 射頻接收機之CMOS低雜訊放大器與CMOS降頻器設計研究

Abstract

本論文主要探討在Millimeter Wave 接收機中兩個重要的高頻電路，一個是超寬頻低雜訊放大器，另一個是超寬頻降頻器。分別在第一部分與第二部份對該兩電路做分析研究。 第一部份:提出利用電晶體本身的寄生電容與transformer 回授的寬頻低雜訊放大器，主要應用頻段在10~18 GHz。該低雜訊放大器藉由在輸入端電晶體加入transformer，利用transformer本身的回授機制與電晶體的寄生電容，能夠在10~18 GHz 頻寬內達到輸入阻抗低於-12dB以下，同時放大器的雜訊指數低於3.5dB。由於在輸入端並無增加任何元件來做輸入阻抗匹配，因此該放大器能夠有較低雜訊指數的表現。此放大器是使用 TSMC 0.18μm mixed signal/RF process，在1.8V電壓下，能提供17dB的增益、最低雜訊指數為2.4dB、-22.6dBm的線性度(IIP3)、功率消耗為37.6mW(緩衝級不算在內)。 第二部份:設計一個應用於W-Band接收機的降頻器，首先會先簡單介紹此W-Band接收機的系統架構，之後將提出所設計的寬頻降頻器。該降頻器輸入頻段為8.7~17.4 GHz，利用LO訊號為17.5 GHz，將此頻段的訊號降頻到0.1~8.8 GHz(IF端)。該降頻器有將近10 GHz的IF頻寬，Conversion Gain 7dB，線性度大於8dBm(IIP3)。此外該降頻器會使用到兩個Balun，分別將RF和LO訊號分成差動訊號，因此在降頻器中加入兩個on chip的Balun，並且將對Balun做探討。同時因為IF端有將近10 GHz的頻寬(單端輸出)，所以必須設計寬頻且高CMRR的IF端電路。該IF端電路有25dB以上的CMRR在0.1~8 GHz頻段內。

This thesis discusses two high frequency circuits applied in millimeter wave receiver. One is an ultra wide band low noise amplifier and the other is a wide band down-converter. The two circuits will be analyzed in the following two parts. In part one, a wide-band (10~18GHz) low noise amplifier (LNA) is proposed. With transformer feedback in the traditional cascode amplifier, good input matching is achieved from 10 GHz to 18 GHz. The noise figure is below 3.5dB over 10-18GHz. There are no additional input-matching elements in the input gate of the cascode amplifier, so that the LNA can achieve lower NF. The LNA is designed based on CMOS TSMC 0.18μm mixed signal/RF process. With 1.8V supply voltage and three stage amplifiers to achieve wider gain bandwidth, the LNA can achieve input-matching of -12dB over the bandwidth; minimum NF 2.4dB; gain (S21) of 17dB and 1dB gain compression (P1dB) at -22.6dBm. The power consumption is 37.6mW (exclude buffer) In part two, a wide band down converter will be designed for W-band receiver. First a W-band receiver architecture will be introduced and one of the down-converter in the receiver will be proposed. This part describes the development of the down-converter, with the RF frequency chosen to be 8.7~17.4 GHz, LO fix at 17.5 GHz and IF close to DC~8.7 GHz. The down converter can achieve about 10 GHz IF bandwidth、Conversion Gain 12dB and IIP3 above 8dBm. There will be two on-chip baluns implemented in the circuit for converting single RF and LO signals to differential signals and the balun will be discussed. Besides the down-converter has 10 GHz IF-bandwidth, the IF stage circuit must provide high CMRR over the bandwidth. In the proposed circuit the IF stage can achieve above 25dB CMRR in 0.1~8 GHz.