可抑制變頻切換突波與靜態鎖定相位誤差之100MHz至1.6GHz輸出時脈範圍之延遲鎖定迴路式時脈產生器

Abstract

在不斷進步的VLSI製程技術的發展下，電路系統的操作頻率與積體電路的積體化不斷的精進，但其同時也增加了積體電路的功率消耗。在低功率消耗的考量之下，若能動態的控制系統操作頻率將可有效的降低系統的功率消耗。

本論文設計一個可以抑制變頻切換突波與靜態鎖定相位誤差之寬範圍延遲鎖定迴路式時脈產生器。架構中使用多組的PFD-CP來增加系統所能產生的乘法倍數個數，並且排除會使系統錯誤的非必要突波；利用pulse reshaper電路來改變相位偵測器的特性曲線，降低延遲鎖定迴路在鎖定時的靜態相位誤差，藉此維持系統在寬範圍操作下的輸出訊號效能。在控制電路的操作下，本時脈產生器可產生8種乘法倍數（1/2~8/2），輸出時脈範圍可由100MHz到1.6GHz。此時脈產生器適合應用在低功率消耗的應用中。

量測結果顯示當系統操作在1.2GHz下，其輸出訊號的峰對峰值抖動為128ps，在1.8V的電源供應下所消耗的功率為63mW，整個系統的下線面積為0.65mm*0.76mm。

The VLSI fabrication process has grown rapidly, it promote the circuit system’s operating frequency and IC integrity. Unfortunately, the power consumption of IC chips has also grown with chip size and circuit operating frequency grown. For low power consumption consideration, dynamically frequency scaling function can decreases the system power consumption. In this thesis, a wide-range, programmable DLL-based clock generator with switching glitch and static phase error reduction function is implemented. Use multi-PFD-CP pairs when switching the feedback signal of DLL can eliminate the undesired glitch and increases the numbers of multiplication factors. Use pulse reshaper to change the characteristic plot of PD to reduce the static phase error of DLL and maintain the output signal performance in wide range operation. With a controller, the clock generator can generate eight scales (1/2~8/2) of output multiplication factors and the frequency ranges from ~100MHz to 1.6GHz. It is suitable for the low power application. Measurement result shows the peak-to peak jitter is 128ps at 1.2GHz. The power consumption of the DLL is 63mW under 1.8V power supply. The chip size is 0.65mm*0.76mm.