雙擴散金氧半場效電晶體崩潰電壓及漏電流之最佳化研究

Abstract

隨著半導體製程的發展，高壓高功率元件已由以閘流體與雙極功率電晶體為主的市場，逐漸發展到現今的高功率金氧半場效電晶體，由於高壓功率金氧半場效電晶體之低成本、切換速度快與其功率消耗較低的優勢，因此，將高壓/高功率元件與傳統互補式金氧半場效電晶體的製程技術整合在一起，多被設計用於控制與承載較高電流且耐高壓的高功率積體電路，已成為今日應用市場上最重要的發展。其中雙擴散汲極金氧半場效電晶體是高壓元件中最早被運用的方式，對於操作電壓在低電壓以下之元件而言，雙擴散汲極金氧半場效電晶體，仍舊是所有高壓元件中的優先選擇。 在本篇論文中，我們首先藉由模擬的方式去探討在原有的製程配方(Recipe)下，變更製程多增加一道離子佈植的條件對雙擴散汲極金氧半場效電晶體在電性上的影響，藉此去了解其發生的物理機制，並將由模擬出的結果及趨勢，選擇最適當的條件以改善元件的特性與效能。從過程中，我們發現將植入能量提高，可以提升元件的耐壓能力，但卻會降低其導通電流；若提高植入劑量，則可以改善其漂移區近似飽和的現象，提高其導通電流，但其崩潰電壓卻會因此降低，且基體電流也因此提高。因此，植入劑量及能量便成為改善元件效能上的平衡機制，同時增加額外一道離子植入條件，來改善基體電流一直無法有效降低的難題，利用離子植入能量與劑量的條件，將是本篇論文嘗試解決問題的方向。最後成功驗證高植能量(400KeV)及植入劑量(6.3×10^12cm-2)與額外的離子植入能量(50KeV)及植入劑量(1.4×10^12cm-2)的條件可以大幅改善元件的特性，不僅緩和了許多的效應，提升崩潰電壓約10%，降低了基體電流約77%，關閉電流降低約34%。在此結果之下，尚可縮小元件的尺寸，增加元件密度，對於類似的元件極具競爭力。

With the progress of integrated circuit technology , high-voltage devices with high power have developed into the market of HV-MOSFETs from the market of thyristors and bipolar power transistors ,which have become the most preferable devices to be integrated with the technology of conventional CMOS due to its low cost, fast switching speed, and low power loss. Hence, HV-MOSFETs are mostly-applied to not only control but also carry the high power ICs with high current nowadays. Integrating high power devices with low power circuit is an important in the marketing of electronic application. The Double-Diffusion Drain MOS ( DDDMOS ) is the first device structure proposed to sustain high drain voltage. DDDMOS is still the first choice for devices operating at low voltage due to its simple process. In this thesis, we focus on the impact of ion implantation condition of original process and extra implantation process on the performance of DDDMOS. Using TCAD simulation tools,it is observed that with the increase of implantation energy, the breakdown voltage increases and the snapback issue is relaxed. However, the saturation current will be degraded due to the formation of non-converted p-type region on the drain surface. If the implant dosage is increased, the quasi-saturation phenomenon at high gate voltage, the driving capability, and the turn-off leakage are all improved, but the breakdown voltage would be degraded, and increase substrate current. So we add the extra surface implantation process to improve the substrate current. These results imply that implantation dose and energy might be the better choice.On the basis of TCAD simulation, the implantation energy was raised to 400 KeV and the implantation dose was changed to 6.3×10^12cm-2 and extra surface implantation energy was 50 KeV and the implantation dose was 1.4×10^12cm-2 .A 10% increase of breakdown voltage and 34% reduction of turn-off current were obtained. Meanwhile the 77% reduction of substrate current was observed due to the extra implantation process. It is expected that with higher energy and dose device performance can be improved furthermore.