奈米互補式金氧半製程下之低漏電源箝制靜電放電防護電路

Abstract

本篇論文主旨在設計奈米互補式金氧半製程下之低漏電電源箝制靜電放電防護電路。其原理為利用電路和元件特性，使電路整體漏電降到最低，但又能具有高水準之靜電放電防護能力。本篇論文分為三大部分，主要透過電路模擬以及實驗的量測來驗證所提出的新型設計。 第一部分是在介紹關於研究穿隧現象(Gate-Tunneling)的演進過程，爾後互補式金氧半製程中，隨著閘極氧化層越薄的情況下此現象有越明顯的趨勢。在過去的研究中已經研究出此穿隧現象(Gate-Tunneling)的機制和相對應之方程式，並且建設穿隧現象(Gate-Tunneling)的模型，應用在先進製程之奈米互補式金氧半製程裡。 第二部份為應用65奈米互補式金氧半製程薄氧化層元件模擬，除了模擬MOS電容閘極漏電的現象之外，之後再進一步探討此種MOS電容應用在傳統電源箝制靜電放電防護電路和新型電源箝制靜電放電防護電路中，MOS電容嚴重漏電對整體電路的影響。在模擬結果中傳統電源箝制靜電放電防護電路因MOS電容漏電的影響，帶來更嚴重的漏電問題。雖然有其他電路方法解決電路漏電問題，但是還是存在著漏電路徑經由MOS電容，此漏電數量還是非常嚴重。此提出新型設計目的就是為了解決漏電問題，在正常的工作下不會有大量漏電的問題，並且在靜電放電轟擊之下亦能適時動作排放靜電放電電流，在模擬結果中此新型的設計是可行的並且具有相當低的漏電流。 第三部份為實際量測結果，所有電路和元件皆以65奈米互補式金氧半製程實現，實驗結果顯示，閘極漏電流的問題已經不能忽略，傳統電源箝制靜電放電防護電路受到MOS電容漏電的影響，有著更嚴重的漏電問題(室溫下約六百一十三微安培)，必須要有所改善。此新型電源箝制靜電放電防護電路可以達到所需的要求，除了有極低的漏電流(室溫下約一百一十六奈安培)之外，亦有非常好的靜電放電防護能力，在人體放電模式靜電放電轟擊超過八千伏特，並且在機器放電模式的靜電放電防護能力約七百五十伏特。

The aim in this thesis is to design the low-leakage power-rail ESD clamp in nanoscale CMOS technology. The principles are using circuit and component characteristics to minimize leakage of the circuit. Besides having the lowest leakage current, it also can have high robustness of ESD protection. This thesis includes three topics; the main parts are through the circuit simulation and experimental measurements to verify the new proposed design. The first part is to introduce the evolution of gate-tunneling research. With the gate-oxide thickness become thinner and thinner in CMOS processes, the phenomena become more and more serious. In the past research, the mechanisms and formulas of gate-tunneling have been observed. The model of gate-tunneling also has been applied into advance CMOS processes. The second part is to simulate circuits and components in the 65-nm CMOS process with thin-oxide devices. Besides simulating the leakage current of MOS capacitor, the further discusses are what it will influence if MOS capacitor is applied to traditional power-rail ESD clamp circuits and new proposed power-rail ESD clamp circuit. In the simulation results, the leakage of MOS capacitor causes incorrect function which causes another leakage path and leak more current in the circuit. Although there have other methods to reduce the leakage current, but there is still have a leakage path through MOS capacitor. However, with a voltage drop across MOS capacitor, the MOS capacitor always leaks some current. The leakage current is still very huge. The new proposed design was designed to have lower leakage current when it is under normal circuit operating conditions and discharge ESD current in time when it is under ESD transient. As the simulation result, the new proposed design has lower leakage current than traditional designs. The third part is measured results. In this thesis, a new low-leakage power-rail ESD clamp circuit designed with the consideration of gate-leakage issue has been proposed and verified in 90-nm and 65-nm CMOS processes. According to the measured results, the gate leakage issue needs to be taken into consideration. The traditional designs have more leakage current because the leakage of MOS capacitor, so the traditional designs can not be used if it is implemented in nanoscale CMOS process with thin-oxide device. The new proposed design has the lowest leakage current (228 nA at 25 oC) and good robustness of ESD tests. It has ESD robustness of over 8 kV in HBM and 750 V in MM.