十億級資料傳輸室內無線SC/OFDM接收器之相位雜訊消除演算法及設計

Abstract

應用於 60GHz 系統的高頻元件需要較好的品質，因為高頻元件的不完美性會對這些系統造成嚴重問題，如：載波頻率飄移（carrier frequency offset）、I/Q 不平衡（I/Q imbalance）及相位雜訊（phase noise）。這篇論文提出一雙模式、低複雜度的相位雜訊消除演算法及其硬體設計。此演算法可以消除高頻相位雜訊，支援正交分頻多工（orthogonal frequency division multiplexing (OFDM)）和單載波（single carrier (SC)）兩種模式，並達 到IEEE 802.15.3c 規格要求。同時，其運算複雜度低，能夠以硬體實現並使用於通訊系統晶片中。 此雙模式相位雜訊消除演算法由「頻域時域複合相位雜訊消除演算法」和「兩階段相位雜訊消除演算法」兩種演算法組成，前者適用於OFDM 模式，後者適用於 SC 模式。在 OFDM 模式，頻域時域複合相位雜訊消除演算法以一頻域演算法消除共同相位誤差（common phase error (CPE)）之效應，再以一時域演算法消除載波間干擾（inter-carrier interference (ICI)）之效應，時域演算法的硬體面積約略等於頻域演算法。針對SC 模式之兩階段相位雜訊消除演算法其99.8%的硬體能與OFDM 模式之頻域演算法共用。 使用65 奈米CMOS 製程，以1.5 奈秒合成硬體，扣除共用的記憶體和快速複利葉轉換（FFT）電路之後，頻域演算法的等效邏輯閘數（gate count)為11.5 萬個，時域演算法為11.9 萬個。在OFDM 模式，當相位雜訊頻寬為12.5MHz、方均根值為15 度，SNR為12dB 時，QPSK 的系統BER 可以達到3.3×10^-4；在SC 模式，當相位雜訊頻寬為12.5MHz、方均根值為8 度，SNR 為12dB 時，QPSK 的系統BER 可以達到8.91×10^-4。

High quality RF devices for 60GHz systems are required because RF device imperfections cause serious problems in these systems, such as carrier frequency offset, I/Q imbalance and phase noise. This thesis proposes a dual mode low complexity phase noise cancellation algorithm and its hardware design for wide bandwidth phase noise cancellation. This algorithm supports both orthogonal frequency division multiplexing (OFDM) mode and single carrier (SC) mode. It achieves the specifications of the IEEE 802.15.3c standard. Most importantly, its low complexity makes it possible to be implemented at baseband receivers. The dual mode algorithm consists of a hybrid domain phase noise cancellation algorithm for OFDM mode and a two-stage phase noise cancellation algorithm for SC mode. In OFDM mode, the hybrid domain phase noise cancellation algorithm comprises a frequency domain algorithm for common phase error (CPE) cancellation and a time domain algorithm for inter-carrier interference (ICI) cancellation. The hardware of the time domain algorithm has about the same size as the hardware of the frequency domain algorithm. 99.8% of the hardware of the two-stage phase noise cancellation algorithm for SC mode can be shared with the frequency domain algorithm for HSI mode. A 65nm CMOS process is applied. Excluding the shared memory and the shared FFT blocks, the gate count of the frequency domain algorithm is 115K and the gate count of the time domain algorithm is 119K when the timing constraint used for the synthesis is 1.5ns. Consider the situation that QPSK is applied and the SNR equals 12dB. For HSI mode, when the bandwidth of phase noise is 12.5MHz and the RMS of phase noise is 15 degrees, the BER of the system is 3.3×10^-4. For SC mode, when the bandwidth of phase noise is 12.5MHz and the RMS of phase noise is 8 degrees, the BER of the system is 8.91×10^-4.