K-Band低電壓互補式金氧半壓控震盪器與除頻器以應用於鎖相迴路之關鍵積體電路設計與分析

Abstract

在此畢業論文裡，一個高效能雙正回授壓控振蕩器和電流模式高頻率除法器並應用於低電壓高頻率的鎖相迴路已經被研究，分析，並且實現。此雙正回授壓控震盪器、電流模式除頻器、以及鎖相迴路電路都操作在K-band的範圍內。此外，本論文也探討了利用先進45-nm製程技術設計的兩組壓控震盪器以及除頻器。本論文主要包含了三大部分:第一，針對K-band CMOS雙正回授壓控震盪器以及電流模式除頻器做研究以及分析。第二，針對所提出之壓控震盪器及電流除頻器應用於低電壓高頻率的鎖相迴路中問題的探討與研究。第三，探討了45-nm planar bulk-CMOS以及45-nm FinFET等不同元件在RF電路中的效能。也利用above-IC電感技術來實現一個high-Q的電感元件並應用於設計電路中。 為使應用於電流模式鎖向迴路，我們設計一個新的雙正回授壓控震盪器並產生輸出射頻電流以輸入電流模式頻率除頻器。雙正回授的概念係利用Colpitts及NMOS cross- coupled pair來增加負電阻及令輸出差模訊號更對稱，用以減少在低電壓狀況下的電流消耗及提高相位雜訊。本電路已完成分析，設計，以及晶片製造。其晶片量測結果顯示，分別在不同電壓1 V、1.1 V和 1.2 V所量到的電流消耗僅為0.78 mA、0.97 mA和1.17 mA。所量測到之相位雜訊在1 V、1.1 V 和1.2 V的不同供給電壓下分別為-104 dBc/Hz、-112 dBc/Hz和-115 dBc/Hz，此結果是在離震盪頻率1-MHz的偏移頻率所量測。此壓控震盪器最好的FOM為-201dBc/Hz。晶片面積為0.47mm2，此面積包含量測銲墊(pads)。 本論文亦提出了一個藕荷電流注入鎖定頻路除頻器。利用電流注入的方式可使電路應用於高頻低電壓的電路環境設計中。並解決了傳統在高頻除頻器過窄的除頻範圍的問題。利用電流注入方式亦可以解決因為高頻RF訊號因為寄生效應而使注入訊號衰減，而導致鎖定範圍變窄的問題。此電路操作於K-band (24-GHz) 0.8-V電壓下，除頻範圍可達4.1GHz(19.5%)，並只消耗的1.51mW。另外，本章節中也發表了為了改善傳統電流模式邏輯(CML)除頻器在低電壓時因為電壓空間不足所造成其電路中之差動對無法順利操作電路，以至於無法正確除頻的問題。利用電流注入的方式，可以讓電路在低電壓下，利用電流來切換開關電路以避免電壓空間不足的問題。且所消耗支功率為1.89mW。所提出之兩電路晶片面積分別為0.23 mm2 及 0.015 mm2，此面積不包含量測銲墊。 利用前述所提出之雙正回授壓控震盪器及電流模式除頻器，設計出0.8-V、24-GHz並只消耗了9.2-mW功率的鎖相迴路。在設計高頻低電壓鎖相迴路中，常因高頻震盪器及高頻除頻器使消耗功率大幅提升，而使得整個電路需要消耗極大功率，而這在目前及未來的通訊應用中，越來越倚賴電池的狀況下極為不利。因此如何降低此關鍵電路的功率消耗便成為一大挑戰。因此利用所提出之電路設計包含雙正回授壓控震盪器及電流模式除頻器，及所提出之適合低電壓操作之電荷幫浦，高頻率相位偵測器等電路所組成。其量測結果顯示，in-band之相位雜訊為-98dBc/Hz，鎖相迴路可調頻範圍為22.6GHz到23.3GHz。所量測之突波強度為-69dBm。最大特點為，其消耗功率僅為9.2 mW，且整個電路操作在0.8-V的低電壓環境下。晶片面積為1 mm2，此面積包含量測銲墊。 在本論文也針對先進製程作一深入探討並比較利用45-nm planar bulk-CMOS及FinFET不同元件所達成的電路表現。並利用WLP製程所製造出的高Q質電感為電路成功的實現兩組不同設計的壓控震盪器及除頻器。利用planar bulk-CMOS 所設計之壓控震盪器及注入鎖定式除頻器在模擬上可操作在24 GHz頻率，操作頻率為0.8V，消耗功率為0.48mW，調頻範圍為22.4GHz至24.6GHz。相位雜訊在1MHz偏移頻率時為-100dBc/Hz。在除頻器的模擬中，在-2dBm的輸入功率下，其鎖定範圍為2GHz。此電路在0.8V的操作電壓下只銷耗了0.32mW。第二組電路係利用45-nm FinFET所設計之壓控震盪器以及除頻器中，亦使用了WLP above-IC電感。此電感能提供高Q值，因此能達到小消耗功率以及低相位雜訊的目標。此電路的模擬結果顯示，在0.8V操作電壓下，壓控震盪器的功率消耗為0.56mW，調頻範圍為23.4GHz至24.6GHz。FinFET 除頻器中，鎖定範圍為1GHz，消耗功率為0.56mW。在量測結果中，因為比利時IMEC製程製造的問題，只成功量測到利用 planar bulk-CMOS所設計之壓控震盪器。其中心頻率為18GHz，相位雜訊為-93dBc/Hz在1MHz的偏移頻率。調頻範圍為17.5GHz至19.2GHz，所消耗之功率在0.8V操作電壓下為0.57mW。 總結本論文的研究成果，並提出數個接續本論文研究方向的研究題目。本論文所提出的各電路，均搭配實驗晶片量測結果以驗證設計之理論，且有相對應的國際旗杆與國際研討會議論文發表。

In this dissertation, a novel double-positive-feedback VCO with current-mode outputs is proposed. The concept of combining the Colpitts and NMOS cross-coupled while reusing the dc bias current is adopted to enhance the phase noise performance and reduce the power consumption. The circuit analysis and methodology are given in this chapter and the performance of VCO is also verified through the experimental results. The fabricated DPF-VCO consumes only 0.78 mA, 0.97 mA, and 1.17 mA under the supply voltage of 1 V, 1.1 V, and 1.2 V, respectively, and the corresponding measured phase noise is -104 dBc/Hz, -112 dBc/Hz, and -115 dBc/Hz at 1-MHz offset frequency. The best FOM of the proposed DPF-VCO is -201 dBc/Hz. The chip area is 0.47mm2 including pads. An innovative coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) frequency divider are proposed. The CCMILFD is composed of two current-mode injection-locked frequency dividers (CMILFDs) and one coupling circuit. A new method of injecting the current signal directly into the divider instead of the voltage signal is adopted in the proposed CMILFD. This reduces the required voltage headroom and solves the problem of poor efficiency associated with voltage-to-current translation in the input stage. In the CICML frequency divider, the switching mechanism is determined by the current and not the voltage signal. The voltage headroom requirement and the switching response time for the devices can be relieved. It can make the whole circuit feasible to be operated in a high frequency band and under a low supply voltage condition. The locking range of the fabricated CCMILFD is 4.1 GHz with the power consumption of 1.51 mW from a power supply of 0.8 V. In the proposed CICML frequency divider, the current-injection interface is applied to the current inputs to make the circuit operated at a higher frequency with low power consumption under a low voltage supply. The operation frequency of the fabricated CICML frequency divider can divide the frequency range from CCMILFD and consume 1.89 mW from a 0.8-V voltage supply. The chip core areas of the CCMILFD and CICML frequency divider without pads are 0.23 mm2 and 0.015 mm2, respectively. The proposed circuits can be operated in a low supply voltage with the advantages of a wider locking range, a higher operation frequency, and lower power consumption. To demonstrate the proposed current-mode methodology and technique for the low-voltage and low-power application, a 0.8-V 24-GHz PLL with 9.2-mW power consumption is designed and proposed. The challenges in implementing a low-voltage RF PLL are on the design of voltage-controlled oscillator (VCO) and high-frequency frequency dividers. With DPF-VCO, the proposed PLL can have good phase noise performance under low voltage. The current-mode output stages used in the VCO are to obtain and propagate output current signals instead of voltage signals to the next stage. For the frequency dividers of the PLL, the CCMILFD and the CICML are used to divide the output frequency of VCO. By means of the current-mode technique, the PLL can provide high quality output signal with low in-band phase noise and low reference spur level operated in a low supply voltage with low power consumption. The measured in-band phase noise of the fabricated PLL is -98dBc/Hz. The locking range of PLL is from 22.6GHz to 23.3GHz and the reference spur level is -69dBm that is 54dB bellow the carrier. The power consumption is 9.2mW under 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation. The chip area is 1mm2 including pads. Two versions of VCO and divider designed by using IMEC planar bulk-CMOS and FinFET technologies are demonstrated and compared. In the high frequency band, quality factors of inductors at high frequency are dominated by the loss to the substrate. In order to obtain a high quality factor, the distance between the substrate and the inductors has to be increased. By means of post processing, the inductors can be realized above the chip in a Wafer Level Packaging (WLP) technology. The inductors are connected to the circuit by means of vertical pillars. The high-Q above-IC inductors are implemented through the IMEC WLP technology which consists of a 5-μm thick electroplated copper layer on an 18-μm low-k dielectric of Benzo-Cyclo-Buthene (BCB). The fabricated bulk-CMOS VCO has been measured. The measured phase noise is -93 dBc/Hz at 1-MHz frequency offset and the measured tuning range is 8.8 %. The power consumption of the bulk-CMOS VCO is 0.56 mW under 0.8-V supply voltage. The experimental results have proved the suitability of 45-nm device in the applications of low power, low voltage, and high frequency range RF ICs.