使用0.18-μm CMOS製程之蕭特基二極體與無失真微波被動元件設計60-GHz雙轉頻收發機

Abstract

適用於短距高速傳輸的60-GHz微波毫米波收發機，近年來大多實現於先進90nm、65 nm、45 nm CMOS製程，由於受限CMOS元件的雜訊指數和崩潰電壓，60-GHz CMOS低雜訊放大器的雜訊指數並未顯著跟隨Scaling Rule的演進而得到大幅的改善，同時60-GHz CMOS功率放大器亦受限於最大輸出功率，造成60-GHz相位陣列系統需要更多組的路徑來提升輸出功率，以克服傳輸路徑的損耗，而CMOS的低功率附加效率更增加整體的直流功耗，使得60-GHz CMOS收發機無法應用於可攜帶式電子產品。相較於CMOS製程，Ⅲ-Ⅴ族的砷化鎵元件先天上具有較低的雜訊指數(NFmin)、較高的線性輸出功率(OP1dB)和功率附加效率(PAE)，因而在電路特性和開發成本的考量下，本論文提出不同於現今CMOS先進製程的60-GHz架構，採用Ⅲ-Ⅴ族的砷化鎵製程於60-GHz功率放大器和低雜訊放大器設計，其餘的射頻前端電路採用標準0.18-μm CMOS晶圓代工的製程，由於0.18-μm CMOS製程具有較低的光罩成本，將可大幅降低60-GHz晶片的研發經費。本論文完成60-GHz前端電路於0.18-μm CMOS製程的實作與驗證。 其中，"蕭特基二極體元件"和"無失真微波被動元件"是實現0.18-μm CMOS 60-GHz雙轉頻收發機的兩個重要關鍵。蕭特基二極體的高截止頻率和低開啟電壓分別提升0.18-μm製程的操作頻率超越CMOS元件的截止頻率，並減少LO訊號驅動收發機所需的功率，此將利於LO產生器整合至60-GHz 0.18-μm CMOS雙轉頻收發機。無失真微波被動元件是利用無失真傳輸線理論的概念來達成面積的縮小化，只要符合無失真傳輸線的要件，依然可以在有損耗的情況下，藉由高介電常數達成縮小化的目的。因而適當設計被動元件直接於矽基板上(~10 歐姆x公分)，其高介電矽材質將有利於元件的縮小。雖然此縮小化的技巧會帶來些許的傳輸損耗，但本文中亦提出步階阻抗式和集總-分布式的設計方法，更加縮短傳輸線的長度，以減緩矽基板和金屬線的損耗。"相位反轉鼠徑耦合器"為主要研究的被動元件，並應用於實際的吉伯特混頻器，結合"步階阻抗式式/集總-分布式"的架構和"契比雪夫"的頻率響應設計，將可同時達成寬頻和縮小化的特性。在本文最後的章節，獨立討論並實作各類高速除頻電路，其中包括"數位式超動態除頻器"和"回授再生式除頻器"，此將利於LO訊號產生器的設計與整合。

Recently, most 60-GHz transceivers have been demonstrated using advanced CMOS technologies, such as 90 nm, 65 nm and 45 nm. Low noise amplifier (LNA) and power amplifiers (PA) are the key components in resisting the high 60-GHz path loss caused by oxygen attenuation. Limited by the maximum breakdown voltage and minimum noise figure (NFmin) of CMOS devices, 60-GHz CMOS PAs possess small output power and low power-added efficiency (PAE) while 60-GHz CMOS LNAs have no significant improvement in noise figure even with advanced CMOS technologies. This impairs the development of 60-GHz portable equipment. Compared with CMOS technologies, III-V GaAs-based technologies inherently have a superior noise figure with low DC power consumption and large linear output power with high PAE. Thus, this dissertation proposes an alternative approach to a 60-GHz transceiver, in which the LNA/PA are realized using III-V GaAs-based technology and the other circuits of the 60-GHz front-end are fully implemented using low-cost 0.18-μm CMOS foundry technology. The latter has been successfully demonstrated in our work. The low photolithography cost of the 0.18-μm CMOS process allows iterations to solve the problem of inaccurate device modeling, greatly reducing the costs in the R&D phase. Two key components of the 60-GHz 0.18-μm CMOS dual-conversion transceiver are the introductions of a Schottky diode and a distortionless microwave passive component. The Schottky diode, with its high cut-off frequency, promotes the speed of the 0.18-μm CMOS technology beyond fT of an MOS device, while its low turn-on voltage alleviates the difficulty of millimeter-wave LO generation with 0.18-μm CMOS technology. Distortionless transmission theory for miniaturization is developed in the passive component design. Size shrinkage by the effective dielectric constant is still preserved even if the attenuation constant coexists. When implementing a microwave component directly on silicon substrate, high silicon dielectric constant is of great benefit in size shrinkage. Although the effect of lossy silicon substrate is induced, step-impedance and lump-distributed techniques are employed in this work to effectively reduce transmission-line length for small silicon-substrate and metal loss. Here, a phase-inverter rat-race coupler with excellent amplitude/phase balance is the main object of study. Incorporating the step-impedance technique with the Chebyshev response, compact size and wide bandwidth can be simultaneously attained in the phase-inverter rat-race coupler. Finally, different kinds of high-speed frequency dividers, such as super-dynamic and regenerative structures, are introduced and discussed.