A NEW FAST ONE-PASS THINNING ALGORITHM AND ITS PARALLEL HARDWARE IMPLEMENTATION

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	CHEN, CS	en_US
dc.contributor.author	TSAI, WH	en_US
dc.date.accessioned	2014-12-08T15:05:33Z	-
dc.date.available	2014-12-08T15:05:33Z	-
dc.date.issued	1990-07-01	en_US
dc.identifier.issn	0167-8655	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4078	-
dc.language.iso	en_US	en_US
dc.title	A NEW FAST ONE-PASS THINNING ALGORITHM AND ITS PARALLEL HARDWARE IMPLEMENTATION	en_US
dc.type	Article	en_US
dc.identifier.journal	PATTERN RECOGNITION LETTERS	en_US
dc.citation.volume	11	en_US
dc.citation.issue	7	en_US
dc.citation.spage	471	en_US
dc.citation.epage	477	en_US
dc.contributor.department	資訊科學與工程研究所	zh_TW
dc.contributor.department	Institute of Computer Science and Engineering	en_US
dc.identifier.wosnumber	WOS:A1990DT24800004	-
dc.citation.woscount	13	-
顯示於類別：	期刊論文