标题: | 在奈米设计绕线中针对效率,可制造性与良率的最佳化 Performance, Manufacturability, and Yield Optimization in Nanometer Design Routing |
作者: | 林彦宏 Lin, Yen-Hung 李毅郎 Li, Yih-Lang 资讯科学与工程研究所 |
关键字: | 史坦那树建构;障碍物;时序;细部绕线;双图案微影;三图案微影;光学接近矫正;Steiner tree construction;Obstacle;Timing;Detailed Routing;Double Patterning;Triple Patterning;Optical Proximity Correction |
公开日期: | 2012 |
摘要: | 随着设计制程进入奈米时代之后, 设计方法的改变加速了晶片生产的时程,但也因此必须在设计的同时额外考虑许多新的议题,藉此改善晶片的效率,可制造性与良率。由于系统单晶片(System-on-Chip)的导入缩短了晶片设计的时程,但同时让传统的史坦那树建构方法遭遇到新的问题:障碍物的出现。一般的史坦那 树建构方法只试图去最小化总线长或者最小化最大延迟时间(Delay),而且无法 有效率地处理非常大的问题。再者,最大延缓时间(Slack)最小化的重要性远超过于最大延迟时间最小化,但是之前的研究很少涉及到这个议题。因此我们提出了ㄧ个以关键性树干为基础的可避开障碍物的直角史坦那树建构方法来考虑上述所提到的议题,并且在建构的同时考虑插入缓冲器所带来的影响,以进一步减少所需要的绕线资源。 当制程进入二十二奈米以下后,传统的光学微影技术与设备已经不敷使用,加上下一代光学微影技术,如E-Beam,发展的迟缓,迫使制造二十二奈米以下的晶片仍然必须使用现有的光学微影技术与设备,于是双图案微影技术(Double Patterning Lithography)甚至三图案微影技术(Triple Patterning Lithography)因此被发明并采用,藉此延伸现有光学微影技术的可制造性。双图案微影技术透过布局分解(Layout Decomposition)将在ㄧ个布局上的图形拆解到两个光罩上,然后再对两个光罩依序地进行曝光,藉着加大最小图案间的距离来加强解析度,进而提升图案的可印刷性。为了顺利进行布局拆解和最小化所需接缝的数量,在布局生成时同时考虑一般设计目标与双图案微影技术势必成为趋势。与双图案微影技术雷同,三图案微影技术则是将在一个布局上的图案拆解到三个光罩上,藉此更进一步的缩小可印刷的最小尺寸。针对于双图案微影技术与三图案微影技术,我们提出了两个模型来描述布局中图案的关系,并且将这两个模型应用在一个细部绕线器中,藉此达到在布局生成时考虑进布局拆解与最小化所需接缝数量的目的。 为了减少光的散射效应(Diffraction)对于曝光效果的不良影响,光学接近矫正 (Optical Proximity Correction)在一般的微影技术中透过改变光罩上的图案,藉此修正可能造成印刷困难的图案,例如线端与弯折的转角,进而使得曝光在晶片上的图案可以更接近光罩上图案的形状。然而,当193奈米光源波长与目标制程的差距越来越大时,光学接近矫正技术势必要在光罩合成时被加以考虑。和双图案微影技术相同,在布局设计时如果可以考虑光学接近矫正技术所带来的影响,将可以提高光学接近矫正技术的效果。因此,除了考虑双图案微影技术之外,我们还同时在细部绕线阶段同时考虑光学接近矫正技术。 实验结果显示,对于史坦那树建构而言,相对于先前的研究或设计方法,我们 的建构方法可以以十分优异的建构速度,得到相等或者是更优异的最大延迟时间与最差延缓时间。对于多图案微影技术而言,相较于先前的设计方法,在相同的绕线区域中,我们可以得到可以完全进行拆解的布局并使用较少的接缝,虽然使用较多的线长与运算时间,但皆在合理的范围之内;而使用贪懒着色法所得到的布局,将会产生无法顺利拆解的图案。实验结果也显示出,相对于只有考虑双图案微影技术的细部绕线,同时考虑光学接近矫正与双图案微影技术的细部绕线,可以得到较佳的边缘位置误差(Edge Placement Error, EPE)。 As very-large-scale integration (VLSI) designs enter the nano-meter area, many methodologies are introduced to shorten the time-to-market or improve the manufacturability of chips; however, the introduced methodologies bring new issues into the design flow. In modern intellectual property (IP)-block-based system-on-chip (SoC) designs, IP cores, logic blocks, and prerouted wires placed in the core before routing significantly lengthen the wires and increase the delays. Previous researches mostly concern on minimizing the maximum delay or total wirelength instead of minimizing the worst negative slack (WNS), which may violate the timing constraints. This issertation proposes an obstacle-avoiding rectilinear Steiner tree (OARST) construction algorithm based on a critical trunk-based tree growth mechanism to minimize the WNS. Moreover, the effects of buffer insertion are further considered when constructing OARSTs, which effectively reduce the total wirelength. The increasing gap between the 193nm wavelength used in current lithography and the patterning requirement used in sub-22nm process nodes requires the development of the next generation lithography. Double patterning lithography (DPL) and even triple patterning lithography (TPL) become a feasible means of increasing the pitch size and further enhancing the resolution and depth of focus by decomposing one layout in a single layer into two and three masks, respectively. DPL requires the layout decomposition assigning two features in one layer to opposite colors (masks) if their spacing is less than the minimum coloring spacing. Similar to DPL, TPL decomposes a layout in one layer into three masks to further decrease the size of the minimum printability features. This dissertation proposes two graphs to model the coloring relations among features of one layer of one layout in terms of DPL and TPL, respectively. To simultaneously consider the layout generation and the effects of DPL/TPL, we implement one detailed router by applying the proposed graph to generate DPL-/TPL-friendly layouts. To diminish the side-effect of the diffraction of the current lithography, the optical proximity correction (OPC) is demanded to improve printability even after adopting DPL. However, the increasing manufacturing gap disallows OPC alone during the mask synthesis. Similar to DPL, physical design automation, especially in the routing stage, needs to consider the lithographic proximity effects to generate layouts with satisfactory printability. Except for DPL, this dissertation also considers the effects of OPC in the detailed routing stage to further improve the printability of advanced process nodes. Experimental results demonstrate that, compared to previous OARST construction, the proposed approaches spend significantly less time to obtain almost equal or better delay and slack. In terms of DPL and TPL, the proposed approaches acquire a decomposable layout with fewer stitches at the cost of the increment of runtime while the greedy ap- proach cannot generate a decomposable layout for all testcases. Compared to DPL-aware detailed routing, one simultaneously considers OPC effects can effectively improve the EPE after OPC. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079455513 http://hdl.handle.net/11536/40920 |
显示于类别: | Thesis |