在奈米設計繞線中針對效率,可製造性與良率的最佳化

Abstract

隨著設計製程進入奈米時代之後， 設計方法的改變加速了晶片生產的時程，但也因此必須在設計的同時額外考慮許多新的議題，藉此改善晶片的效率，可製造性與良率。由於系統單晶片(System-on-Chip)的導入縮短了晶片設計的時程，但同時讓傳統的史坦那樹建構方法遭遇到新的問題：障礙物的出現。一般的史坦那 樹建構方法只試圖去最小化總線長或者最小化最大延遲時間(Delay)，而且無法 有效率地處理非常大的問題。再者，最大延緩時間(Slack)最小化的重要性遠超過於最大延遲時間最小化，但是之前的研究很少涉及到這個議題。因此我們提出了ㄧ個以關鍵性樹幹為基礎的可避開障礙物的直角史坦那樹建構方法來考慮上述所提到的議題，並且在建構的同時考慮插入緩衝器所帶來的影響，以進一步減少所需要的繞線資源。

當製程進入二十二奈米以下後，傳統的光學微影技術與設備已經不敷使用，加上下一代光學微影技術，如E-Beam，發展的遲緩，迫使製造二十二奈米以下的晶片仍然必須使用現有的光學微影技術與設備，於是雙圖案微影技術(Double Patterning Lithography)甚至三圖案微影技術(Triple Patterning Lithography)因此被發明並採用，藉此延伸現有光學微影技術的可製造性。雙圖案微影技術透過佈局分解(Layout Decomposition)將在ㄧ個佈局上的圖形拆解到兩個光罩上，然後再對兩個光罩依序地進行曝光，藉著加大最小圖案間的距離來加強解析度，進而提升圖案的可印刷性。為了順利進行佈局拆解和最小化所需接縫的數量，在佈局生成時同時考慮一般設計目標與雙圖案微影技術勢必成為趨勢。與雙圖案微影技術雷同，三圖案微影技術則是將在一個佈局上的圖案拆解到三個光罩上，藉此更進一步的縮小可印刷的最小尺寸。針對於雙圖案微影技術與三圖案微影技術，我們提出了兩個模型來描述佈局中圖案的關係，並且將這兩個模型應用在一個細部繞線器中，藉此達到在佈局生成時考慮進佈局拆解與最小化所需接縫數量的目的。

為了減少光的散射效應(Diffraction)對於曝光效果的不良影響，光學接近矯正 (Optical Proximity Correction)在一般的微影技術中透過改變光罩上的圖案，藉此修正可能造成印刷困難的圖案，例如線端與彎折的轉角，進而使得曝光在晶片上的圖案可以更接近光罩上圖案的形狀。然而，當193奈米光源波長與目標製程的差距越來越大時，光學接近矯正技術勢必要在光罩合成時被加以考慮。和雙圖案微影技術相同，在佈局設計時如果可以考慮光學接近矯正技術所帶來的影響，將可以提高光學接近矯正技術的效果。因此，除了考慮雙圖案微影技術之外，我們還同時在細部繞線階段同時考慮光學接近矯正技術。

實驗結果顯示，對於史坦那樹建構而言，相對於先前的研究或設計方法，我們 的建構方法可以以十分優異的建構速度，得到相等或者是更優異的最大延遲時間與最差延緩時間。對於多圖案微影技術而言，相較於先前的設計方法，在相同的繞線區域中，我們可以得到可以完全進行拆解的佈局並使用較少的接縫，雖然使用較多的線長與運算時間，但皆在合理的範圍之內；而使用貪懶著色法所得到的佈局，將會產生無法順利拆解的圖案。實驗結果也顯示出，相對於只有考慮雙圖案微影技術的細部繞線，同時考慮光學接近矯正與雙圖案微影技術的細部繞線，可以得到較佳的邊緣位置誤差(Edge Placement Error, EPE)。

As very-large-scale integration (VLSI) designs enter the nano-meter area, many methodologies are introduced to shorten the time-to-market or improve the manufacturability of chips; however, the introduced methodologies bring new issues into the design flow. In modern intellectual property (IP)-block-based system-on-chip (SoC) designs, IP cores, logic blocks, and prerouted wires placed in the core before routing significantly lengthen the wires and increase the delays. Previous researches mostly concern on minimizing the maximum delay or total wirelength instead of minimizing the worst negative slack (WNS), which may violate the timing constraints. This issertation proposes an obstacle-avoiding rectilinear Steiner tree (OARST) construction algorithm based on a critical trunk-based tree growth mechanism to minimize the WNS. Moreover, the effects of buffer insertion are further considered when constructing OARSTs, which effectively reduce the total wirelength.

The increasing gap between the 193nm wavelength used in current lithography and the patterning requirement used in sub-22nm process nodes requires the development of the next generation lithography. Double patterning lithography (DPL) and even triple patterning lithography (TPL) become a feasible means of increasing the pitch size and further enhancing the resolution and depth of focus by decomposing one layout in a single layer into two and three masks, respectively. DPL requires the layout decomposition assigning two features in one layer to opposite colors (masks) if their spacing is less than the minimum coloring spacing. Similar to DPL, TPL decomposes a layout in one layer into three masks to further decrease the size of the minimum printability features. This dissertation proposes two graphs to model the coloring relations among features of one layer of one layout in terms of DPL and TPL, respectively. To simultaneously consider the layout generation and the effects of DPL/TPL, we implement one detailed router by applying the proposed graph to generate DPL-/TPL-friendly layouts.

To diminish the side-effect of the diffraction of the current lithography, the optical proximity correction (OPC) is demanded to improve printability even after adopting DPL. However, the increasing manufacturing gap disallows OPC alone during the mask synthesis. Similar to DPL, physical design automation, especially in the routing stage, needs to consider the lithographic proximity effects to generate layouts with satisfactory printability. Except for DPL, this dissertation also considers the effects of OPC in the detailed routing stage to further improve the printability of advanced process nodes.

Experimental results demonstrate that, compared to previous OARST construction, the proposed approaches spend significantly less time to obtain almost equal or better delay and slack. In terms of DPL and TPL, the proposed approaches acquire a decomposable layout with fewer stitches at the cost of the increment of runtime while the greedy ap- proach cannot generate a decomposable layout for all testcases. Compared to DPL-aware detailed routing, one simultaneously considers OPC effects can effectively improve the EPE after OPC.