12位元200百萬赫芝具部份隨機匹配的互補式金氧半導體數位類比轉換器

Abstract

高速數位類比轉換器是目前高效能系統,如資料通訊系統、電腦系統、高畫質電視、數位電視中不可缺少的主要電路。然而電流驅動式數位類比轉換器因製程造成電流源不匹配效應往往會限制靜態與動態線性度。本論文設計一個簡單的隨機架構去改善製程的不匹配。我們利用多輸入單輸出多工器架構再配合隨機產生器讓原本固定的線路可以隨機改變,再配合特殊的電流源開關的佈局去改善不同製程的改變,藉此方法打亂諧波,將能量平均分散到noise floor而增加SFDR。 本論文為配合上述簡單隨機架構的一個12位元200MHz數位類比轉換器,數位類比轉換器電路的實現,用切換式電流源式是一個很好的實現方法。數位類比轉換器中包含在較低的4位元為2進位權重架構和較高的8位元為含有隨機匹配的溫度計編碼架構。設計需考量為增進數位類比轉換器的動態效能及提高解析度與元件間的匹配,因而使用了抑制突波的栓鎖器和特殊的佈局,來增加效能。同時也考量了在佈局繞線時產生的寄生電容,所造成速度還有信號不同步的效應。採用TSMC 0.18 µm 1P6M mixed‐signal CMOS 製程來實現，整體晶片面積為0.9022mm2。

High speed digital-to-analog converters (DACs) are very important blocks of nowadays high-performance systems, such as data communication links using multilevel signaling, computer systems, HDTV and digital TV. However, these current-steering DACs suffer from the element mismatch of technologies, which limits both the static and dynamic performance. This thesis proposes a simple random structure to improve the element mismatch . A multiplexer with 4-bit input and 4-bit output was implemented to perform the random selection. The random generator controls the selection of the element in the MSB part so that the harmonics caused by mismatch can be attenuated. The simple random structure can be used to randomize tones such that spurious-free dynamic range is increased. A special geometrical arrangement of unit cells in the current sources of the MSB, along with a new matrix sequence, results in full cancellation of gradient errors. The thesis presents a 12-bit 200MHz digital-to-analog-converter (DAC) by using a current-steering architecture. The output of the DAC does not require an extra output buffer to convert I to V so as to achieve lower power consumption, and to suit for high speed and high resolution application. The current steering DAC needs to deal with the issue of the current source mismatch due to process fabrication. Therefore, current sources are first optimized by transistor size to reduce non-ideal integral nonlinearity (INL) and differential nonlinearity (DNL) effects on static performance. To reduce non-ideal glitch effects, binary-order decision circuits are implemented in the current-steering DAC to allow only one current source opened every time for better performance. Combined with optimized switching sequence and symmetric current source array arranged as a two-dimensional common centroid floor plan, gradient effects and symmetric errors can be further decreased. The 12-bit digital-to-analog converter was fabricated in a TSMC 0.18μm CMOS technology. It is based on a current steering dual segment with both thermometer and binary coded 8+4 architecture.