标题: 12位元200百万赫芝具部份随机匹配的互补式金氧半导体数位类比转换器
A 12-bit 200MSample/s Current-Steering CMOS D/A Converter with Partial Random Matching
作者: 林国智
Lin, Kuo-Chih
洪崇智
陈绍基
Hung, Chung-Chih
Chen, Sau-GEE
电机学院电子与光电学程
关键字: 数位类比转换器;High speed digital-to-analog converters
公开日期: 2011
摘要: 高速数位类比转换器是目前高效能系统,如资料通讯系统、电脑系统、高画质电视、数位电视中不可缺少的主要电路。然而电流驱动式数位类比转换器因制程造成电流源不匹配效应往往会限制静态与动态线性度。本论文设计一个简单的随机架构去改善制程的不匹配。我们利用多输入单输出多工器架构再配合随机产生器让原本固定的线路可以随机改变,再配合特殊的电流源开关的布局去改善不同制程的改变,藉此方法打乱谐波,将能量平均分散到noise floor而增加SFDR。
本论文为配合上述简单随机架构的一个12位元200MHz数位类比转换器,数位类比转换器电路的实现,用切换式电流源式是一个很好的实现方法。数位类比转换器中包含在较低的4位元为2进位权重架构和较高的8位元为含有随机匹配的温度计编码架构。设计需考量为增进数位类比转换器的动态效能及提高解析度与元件间的匹配,因而使用了抑制突波的栓锁器和特殊的布局,来增加效能。同时也考量了在布局绕线时产生的寄生电容,所造成速度还有信号不同步的效应。采用TSMC 0.18 µm 1P6M mixed‐signal CMOS 制程來实现,整体晶片面积为0.9022mm2。
High speed digital-to-analog converters (DACs) are very important blocks of nowadays high-performance systems, such as data communication links using multilevel signaling, computer systems, HDTV and digital TV. However, these current-steering DACs suffer from the element mismatch of technologies, which limits both the static and dynamic performance. This thesis proposes a simple random structure to improve the element mismatch . A multiplexer with 4-bit input and 4-bit output was implemented to perform the random selection. The random generator controls the selection of the element in the MSB part so that the harmonics caused by mismatch can be attenuated. The simple random structure can be used to randomize tones such that spurious-free dynamic range is increased. A special geometrical arrangement of unit cells in the current sources of the MSB, along with a new matrix sequence, results in full cancellation of gradient errors.
The thesis presents a 12-bit 200MHz digital-to-analog-converter (DAC) by using a current-steering architecture. The output of the DAC does not require an extra output buffer to convert I to V so as to achieve lower power consumption, and to suit for high speed and high resolution application.
The current steering DAC needs to deal with the issue of the current source mismatch due to process fabrication. Therefore, current sources are first optimized by transistor size to reduce non-ideal integral nonlinearity (INL) and differential nonlinearity (DNL) effects on static performance. To reduce non-ideal glitch effects, binary-order decision circuits are implemented in the current-steering DAC to allow only one current source opened every time for better performance. Combined with optimized switching sequence and symmetric current source array arranged as a two-dimensional common centroid floor plan, gradient effects and symmetric errors can be further decreased.
The 12-bit digital-to-analog converter was fabricated in a TSMC 0.18μm CMOS technology. It is based on a current steering dual segment with both thermometer and binary coded 8+4 architecture.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079467508
http://hdl.handle.net/11536/40971
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