一個兼具高速及小面積之JPEG2000平行區塊編碼器

Abstract

隨著網際網路和數位相機快速發展，靜態數位影像廣泛地使用於儲存與傳輸媒介。JPEG2000 是一種較新的靜態影像壓縮標準，它比目前使用的JPEG標準有更好的壓縮率，並且提供很多實用特徵。然而這些有用特徵相對的也需要更複雜的運算量與硬體資源。對於JPEG2000編碼器而言，EBCOT Tier-1的Context Formation Encoder是複雜度最高的模組。為了要改善它的效能，Pass-Parallel 架構是目前最有效率的方法之一。在本論文中，我們提出一個高效能且低功率的JPEG2000 Context Formation 方塊編碼器架構。我們藉由三種加速方法並使用管線化技巧來實現新的硬體架構。使用Dual Column Pass1 generation method，Pass-Parallel Column-Based區塊編碼器所需的context window與目前存在的技術比較，面積可降低25%。使用Dual Column Pass1 generation method，all coding pass and significance change generation method 和 sample-parallel column-based coding method，可將整個系統架構的critical path降低。所提的新硬體架構可加快運算效率和減少編碼所需的硬體電路。最後我們利用Verilog硬體描述語言描述我們的架構並且使用Synopsys Design Compiler以TSMC CMOS 0.25μm製程合成後，pre-layout晶片面積大小為 40037μm2，工作頻率可以到達330 MHz，處理一張2304 × 1728的灰階影像時，編碼時間為0.021秒。

As the prompt development of Internet and digital still camera (DSC), still image is broadly used as storage and transmission contents. JPEG2000 is a relatively new still image compression standard. It has better compression performance than conventional JPEG standard, and it provides many useful features. However, these features require more complex computations and hardware resources. The Context Formation Encoder of EBCOT tire-1 is of high complexity in a JPEG2000 encoder. To improve performance, the Pass-Parallel architecture is one of the most efficient methods. In this thesis, a high performance and low-power hardware architecture design of Context Formation encoder for JPEG2000 is proposed. The new hardware architecture is implemented by three speedup methods and pipeline technique. The area of context window of Pass-Parallel Column-Based context formation encoder is reduced by 25% using the proposed Dual Column Pass1 generation method in comparison with existing techniques. The critical path of overall system architecture is reduced employing dual column pass1 generation, all coding pass and significance change generation method and sample-parallel column-based coding method. The new architecture is proposed to improve the computation efficiency and reduce hardware area in pass coding operations. Finally, Our design is described with Verilog HDL code and synthesized by Synopsys Design Compiler using TSMC CMOS 0.25μm process. The pre-layout synthesized area is 40037 μm2. In our simulation, the operation clock frequency can reach 330 MHz. With this clock frequency, it needs 0.021 second to encode an image with 2304 x 1728 image size.